A radix-2/3/22/23 MDC architecture for variable-length FFT processors

Hsin Fu Luo, Ming Der Shieh, Kun Hsien Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A radix-2/3/22/23 multi-path delay commutator (MDC) architecture for pipelined shared-memory fast Fourier transform (FFT) processors is proposed. By using an effective memory addressing scheme, the original processing and control characteristics of the 2m-point FFT processor are retained when processing 3·2m-point FFT, where m is an integer. The proposed variable-length FFT processor can thus be implemented more efficiently.

Original languageEnglish
Title of host publication2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages180-181
Number of pages2
ISBN (Electronic)9781479987443
DOIs
Publication statusPublished - 2015 Aug 20
Event2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015 - Taipei, Taiwan
Duration: 2015 Jun 62015 Jun 8

Publication series

Name2015 IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015

Other

Other2nd IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2015
CountryTaiwan
CityTaipei
Period15-06-0615-06-08

All Science Journal Classification (ASJC) codes

  • Artificial Intelligence
  • Computer Networks and Communications
  • Electrical and Electronic Engineering
  • Instrumentation
  • Media Technology

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