A real-time systolic array for distance transformation

Dyi Long Yang; Chin Hsing Chen

doi:10.1109/ICPR.1994.577195

A real-time systolic array for distance transformation

Dyi Long Yang
, Chin Hsing Chen

Institute of Computer and Communication Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper proposes a systolic array for weighted DT. For an 512×512 image, the design presented in this paper needs only 0.6 ms to complete the DT, which outperforms current existing designs. The architecture is modular and regular, and well suited to VLSI implementation. Both the time and processor complexity of the architecture are linear, to the image size. For a column array processor to perform at the above speed. its hardware cost is about 52 times as expensive as our design.

Original language	English
Title of host publication	Proceedings - International Conference on Pattern Recognition
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	342-344
Number of pages	3
ISBN (Electronic)	0818662751
DOIs	https://doi.org/10.1109/ICPR.1994.577195
Publication status	Published - 1994
Event	12th IAPR International Conference on Pattern Recognition - Conference C: Signal Processing - Conference D: Parallel Computing, ICPR 1994 - Jerusalem, Israel Duration: 1994 Oct 9 → 1994 Oct 13

Publication series

Name	Proceedings - International Conference on Pattern Recognition
Volume	3
ISSN (Print)	1051-4651

Conference

Conference	12th IAPR International Conference on Pattern Recognition - Conference C: Signal Processing - Conference D: Parallel Computing, ICPR 1994
Country/Territory	Israel
City	Jerusalem
Period	94-10-09 → 94-10-13

All Science Journal Classification (ASJC) codes

Computer Vision and Pattern Recognition

Access to Document

10.1109/ICPR.1994.577195

Cite this

@inproceedings{eab4428319e24cb3a509d3ac432c9f04,

title = "A real-time systolic array for distance transformation",

abstract = "This paper proposes a systolic array for weighted DT. For an 512×512 image, the design presented in this paper needs only 0.6 ms to complete the DT, which outperforms current existing designs. The architecture is modular and regular, and well suited to VLSI implementation. Both the time and processor complexity of the architecture are linear, to the image size. For a column array processor to perform at the above speed. its hardware cost is about 52 times as expensive as our design. ",

author = "Yang, \{Dyi Long\} and Chen, \{Chin Hsing\}",

note = "Publisher Copyright: {\textcopyright} 1994 IEEE.; 12th IAPR International Conference on Pattern Recognition - Conference C: Signal Processing - Conference D: Parallel Computing, ICPR 1994 ; Conference date: 09-10-1994 Through 13-10-1994",

year = "1994",

doi = "10.1109/ICPR.1994.577195",

language = "English",

series = "Proceedings - International Conference on Pattern Recognition",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "342--344",

booktitle = "Proceedings - International Conference on Pattern Recognition",

address = "United States",

}

Yang, DL & Chen, CH 1994, A real-time systolic array for distance transformation. in Proceedings - International Conference on Pattern Recognition. Proceedings - International Conference on Pattern Recognition, vol. 3, Institute of Electrical and Electronics Engineers Inc., pp. 342-344, 12th IAPR International Conference on Pattern Recognition - Conference C: Signal Processing - Conference D: Parallel Computing, ICPR 1994, Jerusalem, Israel, 94-10-09. https://doi.org/10.1109/ICPR.1994.577195

A real-time systolic array for distance transformation. / Yang, Dyi Long; Chen, Chin Hsing.
Proceedings - International Conference on Pattern Recognition. Institute of Electrical and Electronics Engineers Inc., 1994. p. 342-344 (Proceedings - International Conference on Pattern Recognition; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A real-time systolic array for distance transformation

AU - Yang, Dyi Long

AU - Chen, Chin Hsing

PY - 1994

Y1 - 1994

N2 - This paper proposes a systolic array for weighted DT. For an 512×512 image, the design presented in this paper needs only 0.6 ms to complete the DT, which outperforms current existing designs. The architecture is modular and regular, and well suited to VLSI implementation. Both the time and processor complexity of the architecture are linear, to the image size. For a column array processor to perform at the above speed. its hardware cost is about 52 times as expensive as our design.

AB - This paper proposes a systolic array for weighted DT. For an 512×512 image, the design presented in this paper needs only 0.6 ms to complete the DT, which outperforms current existing designs. The architecture is modular and regular, and well suited to VLSI implementation. Both the time and processor complexity of the architecture are linear, to the image size. For a column array processor to perform at the above speed. its hardware cost is about 52 times as expensive as our design.

UR - https://www.scopus.com/pages/publications/85027591101

UR - https://www.scopus.com/pages/publications/85027591101#tab=citedBy

U2 - 10.1109/ICPR.1994.577195

DO - 10.1109/ICPR.1994.577195

M3 - Conference contribution

AN - SCOPUS:85027591101

T3 - Proceedings - International Conference on Pattern Recognition

SP - 342

EP - 344

BT - Proceedings - International Conference on Pattern Recognition

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 12th IAPR International Conference on Pattern Recognition - Conference C: Signal Processing - Conference D: Parallel Computing, ICPR 1994

Y2 - 9 October 1994 through 13 October 1994

ER -

A real-time systolic array for distance transformation

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