A reconfigurable arithmetic unit array architecture for DSP applications

Jer Min Jou, Chien Ming Sun, Chen Yen Lin, Yun Lung Lee, Yuan Long Jeang

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)


In this paper, we propose a novel reconfigurable arithmetic unit (RAU) array architecture that is composed of sixteen 8-bit reconfigurable Booth multiply-accumulates (RBM), which has higher performance and is more flexible than the traditional arithmetic unit. The RAU array has the ability to handle 8-bit, 16-bit and 32-bit arithmetic operations and to execute full or partial data flow of DSP applications. It can support 22 kinds of functions and can be used as a co-processing unit or an arithmetic unit in general-propose processors. The experimental results indicated the maximum operation frequency of RAU array that is synthesized in VIRTEX II xc2v3000-4ff 1152 FPGA device is 50.73MHz. For 8-bit 8-tap and 16-bit 8-tap convolution computation, the execution time is 8.4ns and 24.4ns, respectively, that is faster than the general reconfigurable DSP architecture [7].

Original languageEnglish
Pages (from-to)175-183
Number of pages9
JournalInternational Journal of Electrical Engineering
Issue number3
Publication statusPublished - 2007 Jun

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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