TY - JOUR
T1 - A Reconfigurable Transient Optimizer Applied to a Four-Phase Buck Converter for Optimizing Both DVS and Load Transient Responses
AU - Wang, Pai Yi
AU - Huang, Yi Wei
AU - Kuo, Tai Haur
N1 - Funding Information:
ACKNOWLEDGMENT The authors would like to acknowledge the chip fabrication support provided by Taiwan Semiconductor Research Institute (TSRI), Taiwan.
Funding Information:
Manuscript received November 30, 2018; revised January 18, 2019; accepted February 9, 2019. Date of publication March 11, 2019; date of current version December 26, 2019. This work was supported in part by the Ministry of Science and Technology of Taiwan and in part by the Hierarchical Green-Energy Materials (Hi-GEM) Research Center, National Cheng Kung University (NCKU). This brief was recommended by Associate Editor H.-J. Chiu. (Corresponding author: Tai-Haur Kuo.) The authors are with the Department of Electrical Engineering, NCKU, Tainan 70101, Taiwan (e-mail: pywang_msic@ee.ncku.edu.tw; ywhuang_msic@ee.ncku.edu.tw; thkuo@ee.ncku.edu.tw).
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2020/1
Y1 - 2020/1
N2 - This brief presents a reconfigurable transient optimizer (RTO) applied to a four-phase buck converter for optimizing both dynamic-voltage-scaling (DVS) and load transient responses to approach the theoretically minimum output-voltage undershoot { \Delta }\text{V}_{\mathrm{US}} , overshoot { \Delta }\text{V}_{\mathrm{OS}} , and settling time \text{t}_{\mathrm{S}}. The DVS and load transients are instantly detected by a voltage sensor and calibrated capacitor-current sensor, respectively. When a large DVS or load transient occurs, the RTO enables all four phases, reconfigures its circuit architecture, and controls the optimal ON-OFF times of the power switches, thereby settling the output voltage in a single ON-OFF switching with { \Delta }\text{V}_{\mathrm{US}} , { \Delta }\text{V}_{\mathrm{OS}} , and \text{t}_{\mathrm{S}} close to their respective theoretical minima. The converter is fabricated in a 0.18- {\mu }\text{m} CMOS process with a 2.3-mm2 chip area. For a 1-to-1.8 V (1.8-to-1 V) DVS transient, the measured { \Delta }\text{V}_{\mathrm{OS}} ( { \Delta }\text{V}_{\mathrm{US}} ) is not observable, while the measured \text{t}_{\mathrm{S}} is 182 ns (192 ns). For a 1.8-A step-up (step-down) load transient, the measured { \Delta }\text{V}_{\mathrm{US}} ( { \Delta }\text{V}_{\mathrm{OS}} ) and \text{t}_{\mathrm{S}} are 56 mV (45 mV) and 85 ns (76 ns), respectively. Compared with other state-of-the-arts, this brief's \text{t}_{\mathrm{S}} in the DVS transient response is the closest to its theoretical minimum, while the ratios of { \Delta }\text{V}_{\mathrm{US}} , { \Delta }\text{V}_{\mathrm{OS}} , and \text{t}_{\mathrm{S}} to their respective theoretical minima in the load transient response are comparable.
AB - This brief presents a reconfigurable transient optimizer (RTO) applied to a four-phase buck converter for optimizing both dynamic-voltage-scaling (DVS) and load transient responses to approach the theoretically minimum output-voltage undershoot { \Delta }\text{V}_{\mathrm{US}} , overshoot { \Delta }\text{V}_{\mathrm{OS}} , and settling time \text{t}_{\mathrm{S}}. The DVS and load transients are instantly detected by a voltage sensor and calibrated capacitor-current sensor, respectively. When a large DVS or load transient occurs, the RTO enables all four phases, reconfigures its circuit architecture, and controls the optimal ON-OFF times of the power switches, thereby settling the output voltage in a single ON-OFF switching with { \Delta }\text{V}_{\mathrm{US}} , { \Delta }\text{V}_{\mathrm{OS}} , and \text{t}_{\mathrm{S}} close to their respective theoretical minima. The converter is fabricated in a 0.18- {\mu }\text{m} CMOS process with a 2.3-mm2 chip area. For a 1-to-1.8 V (1.8-to-1 V) DVS transient, the measured { \Delta }\text{V}_{\mathrm{OS}} ( { \Delta }\text{V}_{\mathrm{US}} ) is not observable, while the measured \text{t}_{\mathrm{S}} is 182 ns (192 ns). For a 1.8-A step-up (step-down) load transient, the measured { \Delta }\text{V}_{\mathrm{US}} ( { \Delta }\text{V}_{\mathrm{OS}} ) and \text{t}_{\mathrm{S}} are 56 mV (45 mV) and 85 ns (76 ns), respectively. Compared with other state-of-the-arts, this brief's \text{t}_{\mathrm{S}} in the DVS transient response is the closest to its theoretical minimum, while the ratios of { \Delta }\text{V}_{\mathrm{US}} , { \Delta }\text{V}_{\mathrm{OS}} , and \text{t}_{\mathrm{S}} to their respective theoretical minima in the load transient response are comparable.
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U2 - 10.1109/TCSII.2019.2904308
DO - 10.1109/TCSII.2019.2904308
M3 - Article
AN - SCOPUS:85077380810
SN - 1549-7747
VL - 67
SP - 52
EP - 56
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 1
M1 - 8664613
ER -