A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered ZrxSi1-xO2 Gate dielectric and improved electrical and hysteresis performance

Chien Hsiung Hung; Shui Jinn Wang; Pang Yi Liu; Chien Hung Wu; Nai Sheng Wu; Hao Ping Yan; Tseng Hsing Lin

doi:10.7567/JJAP.56.04CG06

A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered Zr_xSi_1-xO₂ Gate dielectric and improved electrical and hysteresis performance

Chien Hsiung Hung, Shui Jinn Wang, Pang Yi Liu, Chien Hung Wu, Nai Sheng Wu, Hao Ping Yan, Tseng Hsing Lin

Institute of Microelectronics

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

The use of co-sputtered zirconium silicon oxide (Zr_xSi_1-xO₂) gate dielectrics to improve the gate controllability of amorphous indium gallium zinc oxide (α-IGZO) thin-film transistors (TFTs) through a room-temperature fabrication process is proposed and demonstrated. With the sputtering power of the SiO2 target in the range of 0-150W and with that of the ZrO2 target kept at 100W, a dielectric constant ranging from approximately 28.1 to 7.8 is obtained. The poly-structure formation immunity of the Zr_xSi_1-xO₂ dielectrics, reduction of the interface trap density suppression, and gate leakage current are examined. Our experimental results reveal that the Zr0.85Si0.15O2 gate dielectric can lead to significantly improved TFT subthreshold swing performance (103mV/dec) and field effect mobility (33.76 cm2V%1 s%1).

Original language	English
Article number	04CG06
Journal	Japanese journal of applied physics
Volume	56
Issue number	4
DOIs	https://doi.org/10.7567/JJAP.56.04CG06
Publication status	Published - 2017 Apr

All Science Journal Classification (ASJC) codes

General Engineering
General Physics and Astronomy

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10.7567/JJAP.56.04CG06

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Hung, C. H., Wang, S. J., Liu, P. Y., Wu, C. H., Wu, N. S., Yan, H. P., & Lin, T. H. (2017). A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered Zr_xSi_1-xO₂ Gate dielectric and improved electrical and hysteresis performance. Japanese journal of applied physics, 56(4), Article 04CG06. https://doi.org/10.7567/JJAP.56.04CG06

@article{04d5b8725a77447089247e6c4d1894d2,

title = "A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered ZrxSi1-xO2 Gate dielectric and improved electrical and hysteresis performance",

abstract = "The use of co-sputtered zirconium silicon oxide (ZrxSi1-xO2) gate dielectrics to improve the gate controllability of amorphous indium gallium zinc oxide (α-IGZO) thin-film transistors (TFTs) through a room-temperature fabrication process is proposed and demonstrated. With the sputtering power of the SiO2 target in the range of 0-150W and with that of the ZrO2 target kept at 100W, a dielectric constant ranging from approximately 28.1 to 7.8 is obtained. The poly-structure formation immunity of the ZrxSi1-xO2 dielectrics, reduction of the interface trap density suppression, and gate leakage current are examined. Our experimental results reveal that the Zr0.85Si0.15O2 gate dielectric can lead to significantly improved TFT subthreshold swing performance (103mV/dec) and field effect mobility (33.76 cm2V%1 s%1).",

author = "Hung, {Chien Hsiung} and Wang, {Shui Jinn} and Liu, {Pang Yi} and Wu, {Chien Hung} and Wu, {Nai Sheng} and Yan, {Hao Ping} and Lin, {Tseng Hsing}",

note = "Publisher Copyright: {\textcopyright} 2017 The Japan Society of Applied Physics.",

year = "2017",

month = apr,

doi = "10.7567/JJAP.56.04CG06",

language = "English",

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journal = "Japanese journal of applied physics",

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Hung, CH, Wang, SJ, Liu, PY, Wu, CH, Wu, NS, Yan, HP & Lin, TH 2017, 'A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered Zr_xSi_1-xO₂ Gate dielectric and improved electrical and hysteresis performance', Japanese journal of applied physics, vol. 56, no. 4, 04CG06. https://doi.org/10.7567/JJAP.56.04CG06

A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered Zr_xSi_1-xO₂ Gate dielectric and improved electrical and hysteresis performance. / Hung, Chien Hsiung; Wang, Shui Jinn; Liu, Pang Yi et al.
In: Japanese journal of applied physics, Vol. 56, No. 4, 04CG06, 04.2017.

Research output: Contribution to journal › Article › peer-review

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T1 - A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered ZrxSi1-xO2 Gate dielectric and improved electrical and hysteresis performance

AU - Hung, Chien Hsiung

AU - Wang, Shui Jinn

AU - Liu, Pang Yi

AU - Wu, Chien Hung

AU - Wu, Nai Sheng

AU - Yan, Hao Ping

AU - Lin, Tseng Hsing

PY - 2017/4

Y1 - 2017/4

N2 - The use of co-sputtered zirconium silicon oxide (ZrxSi1-xO2) gate dielectrics to improve the gate controllability of amorphous indium gallium zinc oxide (α-IGZO) thin-film transistors (TFTs) through a room-temperature fabrication process is proposed and demonstrated. With the sputtering power of the SiO2 target in the range of 0-150W and with that of the ZrO2 target kept at 100W, a dielectric constant ranging from approximately 28.1 to 7.8 is obtained. The poly-structure formation immunity of the ZrxSi1-xO2 dielectrics, reduction of the interface trap density suppression, and gate leakage current are examined. Our experimental results reveal that the Zr0.85Si0.15O2 gate dielectric can lead to significantly improved TFT subthreshold swing performance (103mV/dec) and field effect mobility (33.76 cm2V%1 s%1).

AB - The use of co-sputtered zirconium silicon oxide (ZrxSi1-xO2) gate dielectrics to improve the gate controllability of amorphous indium gallium zinc oxide (α-IGZO) thin-film transistors (TFTs) through a room-temperature fabrication process is proposed and demonstrated. With the sputtering power of the SiO2 target in the range of 0-150W and with that of the ZrO2 target kept at 100W, a dielectric constant ranging from approximately 28.1 to 7.8 is obtained. The poly-structure formation immunity of the ZrxSi1-xO2 dielectrics, reduction of the interface trap density suppression, and gate leakage current are examined. Our experimental results reveal that the Zr0.85Si0.15O2 gate dielectric can lead to significantly improved TFT subthreshold swing performance (103mV/dec) and field effect mobility (33.76 cm2V%1 s%1).

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A room temperature process for the fabrication of amorphous indium gallium zinc oxide thin-film transistors with co-sputtered Zr_xSi_1-xO₂ Gate dielectric and improved electrical and hysteresis performance

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