Abstract
A novel run-pause-resume (RPR) debug methodology that can achieve complete cycle-level granularity of debug resolution for multiple clock domain systems is proposed. With this methodology one can pause the normal operation of a system at any cycle of any clock domain and resume the system without causing any data invalidation problem. Bidirectional transactions among different clock domains are analyzed and supported with this methodology. A debug platform with both breakpoint-setup software and clock-gating hardware is developed. The former allows the user to setup the breakpoint and calculate the exact time to transmit the pause control signal. The latter converts the pause signal to appropriate gating signals for the circuits under debug and the clock domain crossing interface. Experimental results show that the hardware area overhead is very small and 100% debug resolution is achieved. The experimented circuits include an industrial JPEG decoder system, several open-source cores and a system containing three clock domains.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 2017 IEEE International Test Conference, ITC 2017 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 1-10 |
| Number of pages | 10 |
| ISBN (Electronic) | 9781538634134 |
| DOIs | |
| Publication status | Published - 2017 Dec 29 |
| Event | 48th IEEE International Test Conference, ITC 2017 - Forth Worth, United States Duration: 2017 Oct 31 → 2017 Nov 2 |
Publication series
| Name | Proceedings - International Test Conference |
|---|---|
| Volume | 2017-December |
| ISSN (Print) | 1089-3539 |
Other
| Other | 48th IEEE International Test Conference, ITC 2017 |
|---|---|
| Country | United States |
| City | Forth Worth |
| Period | 17-10-31 → 17-11-02 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Applied Mathematics
Cite this
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A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems. / Hong, Shuo Lian; Lee, Kuen-Jong.
Proceedings - 2017 IEEE International Test Conference, ITC 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 1-10 (Proceedings - International Test Conference; Vol. 2017-December).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems
AU - Hong, Shuo Lian
AU - Lee, Kuen-Jong
PY - 2017/12/29
Y1 - 2017/12/29
N2 - A novel run-pause-resume (RPR) debug methodology that can achieve complete cycle-level granularity of debug resolution for multiple clock domain systems is proposed. With this methodology one can pause the normal operation of a system at any cycle of any clock domain and resume the system without causing any data invalidation problem. Bidirectional transactions among different clock domains are analyzed and supported with this methodology. A debug platform with both breakpoint-setup software and clock-gating hardware is developed. The former allows the user to setup the breakpoint and calculate the exact time to transmit the pause control signal. The latter converts the pause signal to appropriate gating signals for the circuits under debug and the clock domain crossing interface. Experimental results show that the hardware area overhead is very small and 100% debug resolution is achieved. The experimented circuits include an industrial JPEG decoder system, several open-source cores and a system containing three clock domains.
AB - A novel run-pause-resume (RPR) debug methodology that can achieve complete cycle-level granularity of debug resolution for multiple clock domain systems is proposed. With this methodology one can pause the normal operation of a system at any cycle of any clock domain and resume the system without causing any data invalidation problem. Bidirectional transactions among different clock domains are analyzed and supported with this methodology. A debug platform with both breakpoint-setup software and clock-gating hardware is developed. The former allows the user to setup the breakpoint and calculate the exact time to transmit the pause control signal. The latter converts the pause signal to appropriate gating signals for the circuits under debug and the clock domain crossing interface. Experimental results show that the hardware area overhead is very small and 100% debug resolution is achieved. The experimented circuits include an industrial JPEG decoder system, several open-source cores and a system containing three clock domains.
UR - http://www.scopus.com/inward/record.url?scp=85046491957&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85046491957&partnerID=8YFLogxK
U2 - 10.1109/TEST.2017.8242077
DO - 10.1109/TEST.2017.8242077
M3 - Conference contribution
AN - SCOPUS:85046491957
T3 - Proceedings - International Test Conference
SP - 1
EP - 10
BT - Proceedings - 2017 IEEE International Test Conference, ITC 2017
PB - Institute of Electrical and Electronics Engineers Inc.
ER -