A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems

Shuo Lian Hong, Kuen-Jong Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A novel run-pause-resume (RPR) debug methodology that can achieve complete cycle-level granularity of debug resolution for multiple clock domain systems is proposed. With this methodology one can pause the normal operation of a system at any cycle of any clock domain and resume the system without causing any data invalidation problem. Bidirectional transactions among different clock domains are analyzed and supported with this methodology. A debug platform with both breakpoint-setup software and clock-gating hardware is developed. The former allows the user to setup the breakpoint and calculate the exact time to transmit the pause control signal. The latter converts the pause signal to appropriate gating signals for the circuits under debug and the clock domain crossing interface. Experimental results show that the hardware area overhead is very small and 100% debug resolution is achieved. The experimented circuits include an industrial JPEG decoder system, several open-source cores and a system containing three clock domains.

Original languageEnglish
Title of host publicationProceedings - 2017 IEEE International Test Conference, ITC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-10
Number of pages10
ISBN (Electronic)9781538634134
DOIs
Publication statusPublished - 2017 Dec 29
Event48th IEEE International Test Conference, ITC 2017 - Forth Worth, United States
Duration: 2017 Oct 312017 Nov 2

Publication series

NameProceedings - International Test Conference
Volume2017-December
ISSN (Print)1089-3539

Other

Other48th IEEE International Test Conference, ITC 2017
CountryUnited States
CityForth Worth
Period17-10-3117-11-02

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

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