TY - GEN
T1 - A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems
AU - Hong, Shuo Lian
AU - Lee, Kuen Jong
N1 - Funding Information:
This work was partially supported by the Ministry of Science and Technology of Taiwan under Contract 105-2221-E-006-242.
Publisher Copyright:
© 2017 IEEE.
PY - 2017/12/29
Y1 - 2017/12/29
N2 - A novel run-pause-resume (RPR) debug methodology that can achieve complete cycle-level granularity of debug resolution for multiple clock domain systems is proposed. With this methodology one can pause the normal operation of a system at any cycle of any clock domain and resume the system without causing any data invalidation problem. Bidirectional transactions among different clock domains are analyzed and supported with this methodology. A debug platform with both breakpoint-setup software and clock-gating hardware is developed. The former allows the user to setup the breakpoint and calculate the exact time to transmit the pause control signal. The latter converts the pause signal to appropriate gating signals for the circuits under debug and the clock domain crossing interface. Experimental results show that the hardware area overhead is very small and 100% debug resolution is achieved. The experimented circuits include an industrial JPEG decoder system, several open-source cores and a system containing three clock domains.
AB - A novel run-pause-resume (RPR) debug methodology that can achieve complete cycle-level granularity of debug resolution for multiple clock domain systems is proposed. With this methodology one can pause the normal operation of a system at any cycle of any clock domain and resume the system without causing any data invalidation problem. Bidirectional transactions among different clock domains are analyzed and supported with this methodology. A debug platform with both breakpoint-setup software and clock-gating hardware is developed. The former allows the user to setup the breakpoint and calculate the exact time to transmit the pause control signal. The latter converts the pause signal to appropriate gating signals for the circuits under debug and the clock domain crossing interface. Experimental results show that the hardware area overhead is very small and 100% debug resolution is achieved. The experimented circuits include an industrial JPEG decoder system, several open-source cores and a system containing three clock domains.
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U2 - 10.1109/TEST.2017.8242077
DO - 10.1109/TEST.2017.8242077
M3 - Conference contribution
AN - SCOPUS:85046491957
T3 - Proceedings - International Test Conference
SP - 1
EP - 10
BT - Proceedings - 2017 IEEE International Test Conference, ITC 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 48th IEEE International Test Conference, ITC 2017
Y2 - 31 October 2017 through 2 November 2017
ER -