A SAR ADC BIST for simplified linearity test

An Sheng Chao, Soon Jyh Chang, Hsin Wen Ting

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A built-in self-test (BIST) scheme to quickly estimate differential nonlinearity (DNL) is proposed. The proposed scheme detects serious code deviation and reduces needed samples. Compared with the conventional code density test, the scheme reduces 97% sample count for a 10-bit approximation register analog-to-digital converters (SAR ADC).

Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2011
Pages146-149
Number of pages4
DOIs
Publication statusPublished - 2011 Dec 28
Event24th IEEE International System on Chip Conference, SOCC 2011 - Taipei, Taiwan
Duration: 2011 Sep 262011 Sep 28

Publication series

NameInternational System on Chip Conference
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Other

Other24th IEEE International System on Chip Conference, SOCC 2011
CountryTaiwan
CityTaipei
Period11-09-2611-09-28

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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  • Cite this

    Chao, A. S., Chang, S. J., & Ting, H. W. (2011). A SAR ADC BIST for simplified linearity test. In Proceedings - IEEE International SOC Conference, SOCC 2011 (pp. 146-149). [6085122] (International System on Chip Conference). https://doi.org/10.1109/SOCC.2011.6085122