A scalable high-precision CMOS max/min circuit using single comparator

Yu Cherng Hung, Bin Da Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A scalable high-precision maximum/minimum circuit is designed. This circuit can be easily configured as maximum or minimum function by an enable signal without modifying the circuit structure and pre-processing input variables. The response time of the circuit is increased linearly with respect to the number of input variables. This circuit has been simulated using 0.5 μm CMOS technology by HSPICE. The results show that a cell can be a winner/loser if its input voltage is larger or smaller than those of other cells by 3 mV.

Original languageEnglish
Title of host publicationAP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages206-209
Number of pages4
ISBN (Print)0780357051, 9780780357051
DOIs
Publication statusPublished - 1999 Jan 1
Event1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of
Duration: 1999 Aug 231999 Aug 25

Publication series

NameAP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Other

Other1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
CountryKorea, Republic of
CitySeoul
Period99-08-2399-08-25

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials

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  • Cite this

    Hung, Y. C., & Liu, B. D. (1999). A scalable high-precision CMOS max/min circuit using single comparator. In AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs (pp. 206-209). [824064] (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.1999.824064