A scalable pipelined architecture for separable 2-D discrete wavelet transform

Jer-Min Jou; Pei Yin Chen; Yeu Horng Shiau; Ming Shiang Liang

doi:10.1109/ASPDAC.1999.759996

A scalable pipelined architecture for separable 2-D discrete wavelet transform

Jer-Min Jou, Pei Yin Chen, Yeu Horng Shiau, Ming Shiang Liang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

This paper presents a highly scalable efficient architecture for separable 2-D Discrete Wavelet Transform (DWT) which is simple, regular, modular and pipelined for die computation of 2-D DWT. Widi these properties, it is easily scalable for different filter lengdis and different octave levels. In addition, the architecture has the characteristics of lower hardware cost, shorter latency, and higher throughput rate.

Original language	English
Title of host publication	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	205-208
Number of pages	4
ISBN (Electronic)	078035012X
DOIs	https://doi.org/10.1109/ASPDAC.1999.759996
Publication status	Published - 1999
Event	4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999 - Wanchai, Hong Kong Duration: 1999 Jan 18 → 1999 Jan 21

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	1999-January

Conference

Conference	4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999
Country/Territory	Hong Kong
City	Wanchai
Period	99-01-18 → 99-01-21

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Computer Science Applications
Computer Graphics and Computer-Aided Design

Access to Document

10.1109/ASPDAC.1999.759996

Cite this

Jou, J.-M., Chen, P. Y., Shiau, Y. H., & Liang, M. S. (1999). A scalable pipelined architecture for separable 2-D discrete wavelet transform. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999 (pp. 205-208). Article 759996 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1999-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.1999.759996

Jou, Jer-Min ; Chen, Pei Yin ; Shiau, Yeu Horng et al. / A scalable pipelined architecture for separable 2-D discrete wavelet transform. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999. Institute of Electrical and Electronics Engineers Inc., 1999. pp. 205-208 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

@inproceedings{94b5ea29e548420c81f2716cde1410ef,

title = "A scalable pipelined architecture for separable 2-D discrete wavelet transform",

abstract = "This paper presents a highly scalable efficient architecture for separable 2-D Discrete Wavelet Transform (DWT) which is simple, regular, modular and pipelined for die computation of 2-D DWT. Widi these properties, it is easily scalable for different filter lengdis and different octave levels. In addition, the architecture has the characteristics of lower hardware cost, shorter latency, and higher throughput rate.",

author = "Jer-Min Jou and Chen, {Pei Yin} and Shiau, {Yeu Horng} and Liang, {Ming Shiang}",

note = "Publisher Copyright: {\textcopyright} 1999 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.; 4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999 ; Conference date: 18-01-1999 Through 21-01-1999",

year = "1999",

doi = "10.1109/ASPDAC.1999.759996",

language = "English",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "205--208",

booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999",

address = "United States",

}

Jou, J-M, Chen, PY, Shiau, YH & Liang, MS 1999, A scalable pipelined architecture for separable 2-D discrete wavelet transform. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999., 759996, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 1999-January, Institute of Electrical and Electronics Engineers Inc., pp. 205-208, 4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999, Wanchai, Hong Kong, 99-01-18. https://doi.org/10.1109/ASPDAC.1999.759996

A scalable pipelined architecture for separable 2-D discrete wavelet transform. / Jou, Jer-Min; Chen, Pei Yin; Shiau, Yeu Horng et al.
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999. Institute of Electrical and Electronics Engineers Inc., 1999. p. 205-208 759996 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1999-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A scalable pipelined architecture for separable 2-D discrete wavelet transform

AU - Jou, Jer-Min

AU - Chen, Pei Yin

AU - Shiau, Yeu Horng

AU - Liang, Ming Shiang

PY - 1999

Y1 - 1999

N2 - This paper presents a highly scalable efficient architecture for separable 2-D Discrete Wavelet Transform (DWT) which is simple, regular, modular and pipelined for die computation of 2-D DWT. Widi these properties, it is easily scalable for different filter lengdis and different octave levels. In addition, the architecture has the characteristics of lower hardware cost, shorter latency, and higher throughput rate.

AB - This paper presents a highly scalable efficient architecture for separable 2-D Discrete Wavelet Transform (DWT) which is simple, regular, modular and pipelined for die computation of 2-D DWT. Widi these properties, it is easily scalable for different filter lengdis and different octave levels. In addition, the architecture has the characteristics of lower hardware cost, shorter latency, and higher throughput rate.

UR - http://www.scopus.com/inward/record.url?scp=84876397150&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84876397150&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.1999.759996

DO - 10.1109/ASPDAC.1999.759996

M3 - Conference contribution

AN - SCOPUS:84876397150

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 205

EP - 208

BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999

Y2 - 18 January 1999 through 21 January 1999

ER -

Jou JM, Chen PY, Shiau YH, Liang MS. A scalable pipelined architecture for separable 2-D discrete wavelet transform. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999. Institute of Electrical and Electronics Engineers Inc. 1999. p. 205-208. 759996. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1109/ASPDAC.1999.759996

A scalable pipelined architecture for separable 2-D discrete wavelet transform

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