A scalable sorting architecture based on maskable WTA/MAX circuit

Shin Hong Ou, Chi Sheng Lin, Bin Da Liu

Research output: Contribution to journalConference articlepeer-review

8 Citations (Scopus)

Abstract

Sorting plays an important role in data and digital signal/image processing. Data become easier to handle with after they are sorted. In this paper we propose a sorter system architecture based upon a novel maskable WTA/MAX circuit design. The proposed sorter is able to sort arbitrary N items of data with simple control mechanism. No extra memory space is needed for storing temporary data during the sorting process. To achieve higher sorting speed, proposed sorting system can be expanded easily by simple hardware cascade. We use an 8-bit sorter design to verify our proposed architecture. Modular concept is adopted and the circuit interconnection is fairly regular. As a result, the bit-length of proposed sorter can be easily augmented to 16-bit or 32-bit. Our sorter chip has been manufactured by TSMC 0.35μm 1P4M process with 32 S/B package. Experimental results show that our chip functions correctly at 50 MHz at 3.3 V power supply voltage.

Original languageEnglish
Pages (from-to)IV/209-IV/212
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
Publication statusPublished - 2002
Event2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States
Duration: 2002 May 262002 May 29

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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