A self-testing and calibration method for embedded successive approximation register ADC

Xuan Lun Huang, Ping Ying Kang, Hsiu Ming Chang, Jiun Lang Huang, Yung Fa Chou, Yung Pin Lee, Ding Ming Kwai, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

This paper presents a self-testing and calibration method for the embedded successive approximation register (SAR) analog-to-digital converter (ADC). We first propose a low cost design-for-test (DfT) technique which tests a SAR ADC by characterizing its digital-to-analog converter (DAC) capacitor array. Utilizing DAC major carrier transition testing, the required analog measurement range is just 4 LSBs; this significantly lowers the test circuitry complexity. Then, we develop a fully-digital missing code calibration technique that utilizes the proposed testing scheme to collect the required calibration information. Simulation results are presented to validate the proposed technique.

Original languageEnglish
Title of host publication2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
Pages713-718
Number of pages6
DOIs
Publication statusPublished - 2011 Mar 28
Event2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011 - Yokohama, Japan
Duration: 2011 Jan 252011 Jan 28

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
CountryJapan
CityYokohama
Period11-01-2511-01-28

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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