A sigma-delta modulation based BIST scheme for A/D converters

Kuen Jong Lee, Soon Jyh Chang, Ruei Shiuan Tzeng

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Abstract

In this paper, a built-in self test (BIST) methodology to measure the four key parameters of A/D converters, namely offset error, gain error, integral nonlinearity error and differential nonlinearity error is proposed. A sigma-delta modulation based signal generator is presented which can concurrently produce analog sinusoidal test stimuli and digital sinusoidal reference signals on chip. By comparing the sinusoidal histogram of the ADC output signals with that of the generated reference digital signals, the parameters can be determined on chip based on some previously-derived equations. This BIST scheme has the following advantages: (1) high accuracy; (2) parameter measurement capability for different frequencies; (3) dynamic sinusoidal testing capability; and (4) low chip area overhead. An 8 bit A/D converter with the proposed BIST architecture is designed and simulated using the TSMC 0.35 μm 1P4M technology. The simulation results show that the test accuracies for the four parameters are all within 0.05 LSB.

Original languageEnglish
Title of host publicationProceedings - 12th Asian Test Symposium, ATS 2003
PublisherIEEE Computer Society
Pages124-127
Number of pages4
ISBN (Electronic)0769519512
DOIs
Publication statusPublished - 2003 Jan 1
Event12th Asian Test Symposium, ATS 2003 - Xi'an, China
Duration: 2003 Nov 162003 Nov 19

Publication series

NameProceedings of the Asian Test Symposium
Volume2003-January
ISSN (Print)1081-7735

Other

Other12th Asian Test Symposium, ATS 2003
CountryChina
CityXi'an
Period03-11-1603-11-19

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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