TY - GEN
T1 - A SIMD-accelerated software rendering pipeline for 3D graphics processing
AU - Yu, Eric Shianda
AU - Chen, Chung Ho
PY - 2012
Y1 - 2012
N2 - This paper presents a SIMD-accelerated software rendering pipeline for 3D graphics processing with multi-core architecture. The multi-core architecture is based on ARMv5 ISA which employs a SIMD unit developed by this work. We also propose a window search bounding box algorithm that can achieve zero failure in pixel tests so that speedup traversal stage is about 20 times faster than the traditional method. Finally, we use an early culling strategy to decrease unnecessary lighting operations.
AB - This paper presents a SIMD-accelerated software rendering pipeline for 3D graphics processing with multi-core architecture. The multi-core architecture is based on ARMv5 ISA which employs a SIMD unit developed by this work. We also propose a window search bounding box algorithm that can achieve zero failure in pixel tests so that speedup traversal stage is about 20 times faster than the traditional method. Finally, we use an early culling strategy to decrease unnecessary lighting operations.
UR - http://www.scopus.com/inward/record.url?scp=84874160501&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84874160501&partnerID=8YFLogxK
U2 - 10.1109/APCCAS.2012.6419066
DO - 10.1109/APCCAS.2012.6419066
M3 - Conference contribution
AN - SCOPUS:84874160501
SN - 9781457717291
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 440
EP - 443
BT - 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
T2 - 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
Y2 - 2 December 2012 through 5 December 2012
ER -