A simulator for evaluating redundancy analysis algorithms of repairable embedded memories

Rei Fu Huang, Jin Fu Li, Jen Chieh Yeh, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

39 Citations (Scopus)

Abstract

We present a simulator for evaluating the redundancy analysis (RA) algorithms. The simulator can calculate the repair rate (the ratio of the number of repaired memories to the number of defective memories) of the given RA algorithm and the associated memory configuration and redundancy structure. With the tool, the user also can easily assess and plan the redundant (spare) elements, and subsequently develop the built-in redundancy analysis (BIRA) algorithms and circuits that are essential for built-in self-repair (BISR) of embedded memories. The simulator has another important feature - it can simulate the sequence of the detected faults in the real order, improving the accuracy of the analysis results.

Original languageEnglish
Title of host publicationProceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing, MTDT 2002
EditorsThomas Wik, Bernard Courtois, Yervant Zorian
PublisherIEEE Computer Society
Pages68-73
Number of pages6
ISBN (Electronic)0769516173
DOIs
Publication statusPublished - 2002 Jan 1
EventIEEE International Workshop on Memory Technology, Design and Testing, MTDT 2002 - Isle of Bendor, France
Duration: 2002 Jul 102002 Jul 12

Publication series

NameRecords of the IEEE International Workshop on Memory Technology, Design and Testing
Volume2002-January
ISSN (Print)1087-4852

Conference

ConferenceIEEE International Workshop on Memory Technology, Design and Testing, MTDT 2002
CountryFrance
CityIsle of Bendor
Period02-07-1002-07-12

All Science Journal Classification (ASJC) codes

  • Media Technology

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