A software-based test methodology for direct-mapped data cache

Yi Cheng Lin, Yi Ying Tsai, Kuen Jong Lee, Cheng Wei Yen, Chung Ho Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)


We present a software-based test methodology that utilizes an on-chip processor to perform test procedures for direct-mapped data cache. The cache system under test is divided into two major groups, namely the memory modules and the logic modules. For the memory modules which include the tag memory, the data memory, and the physical address tag memory, systematic procedures to transform a widely-used March algorithm into various executable instruction sequences are developed. For the logic modules, extensive analysis on the functions as well as the structures (architecture, RTL, and gate-level) of these modules is carried out and effective test instruction sequences based on the analysis are derived. A 100% fault coverage for six conventional RAM fault models and 99.13% test efficiency for single stuck-at fault model are obtained on a real 32-bit RISC processor. These results validate the viability and effectiveness of the proposed methodology for data-cache testing.

Original languageEnglish
Title of host publicationProceedings of the 17th Asian Test Symposium, ATS 2008
Number of pages6
Publication statusPublished - 2008
Event17th Asian Test Symposium, ATS 2008 - Sapporo, Japan
Duration: 2008 Nov 242008 Nov 27

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735


Other17th Asian Test Symposium, ATS 2008

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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