TY - GEN
T1 - A software/hardware co-debug platform for multi-core systems
AU - Lee, Kuen-Jong
AU - Su, Alan
AU - Chen, Long Feng
AU - Jhou, Jia Wei
AU - Kuo, Jiff
AU - Liu, Mark
PY - 2011/12/1
Y1 - 2011/12/1
N2 - In this paper we present a software/hardware co-debug platform to deal with the various debug problems in multiple-core SOC systems with multiple-clock domains. This platform allows designers to debug embedded processors, buses, IP cores, as well as the application programs being developed. It can be used at various design and manufacturing stages including component development, hardware/software co-design, system prototyping, and post-silicon debugging. Three major mechanisms are integrated into this platform, namely a software debug mechanism for multi-core programming, an on-chip hardware debug mechanism for various hardware IPs, and a two-way cross trigger mechanism to synchronize the debug processes of software and hardware. Experimental results on a FPGA prototyping board demonstrate the effectiveness and efficiency of this platform in identifying the root causes of failures for multiple-core SOC systems with multiple-clock domains.
AB - In this paper we present a software/hardware co-debug platform to deal with the various debug problems in multiple-core SOC systems with multiple-clock domains. This platform allows designers to debug embedded processors, buses, IP cores, as well as the application programs being developed. It can be used at various design and manufacturing stages including component development, hardware/software co-design, system prototyping, and post-silicon debugging. Three major mechanisms are integrated into this platform, namely a software debug mechanism for multi-core programming, an on-chip hardware debug mechanism for various hardware IPs, and a two-way cross trigger mechanism to synchronize the debug processes of software and hardware. Experimental results on a FPGA prototyping board demonstrate the effectiveness and efficiency of this platform in identifying the root causes of failures for multiple-core SOC systems with multiple-clock domains.
UR - http://www.scopus.com/inward/record.url?scp=84860876877&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84860876877&partnerID=8YFLogxK
U2 - 10.1109/ASICON.2011.6157171
DO - 10.1109/ASICON.2011.6157171
M3 - Conference contribution
AN - SCOPUS:84860876877
SN - 9781612841908
T3 - Proceedings of International Conference on ASIC
SP - 259
EP - 262
BT - Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011
T2 - 2011 IEEE 9th International Conference on ASIC, ASICON 2011
Y2 - 25 October 2011 through 28 October 2011
ER -