A software/hardware co-debug platform for multi-core systems

Kuen-Jong Lee, Alan Su, Long Feng Chen, Jia Wei Jhou, Jiff Kuo, Mark Liu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper we present a software/hardware co-debug platform to deal with the various debug problems in multiple-core SOC systems with multiple-clock domains. This platform allows designers to debug embedded processors, buses, IP cores, as well as the application programs being developed. It can be used at various design and manufacturing stages including component development, hardware/software co-design, system prototyping, and post-silicon debugging. Three major mechanisms are integrated into this platform, namely a software debug mechanism for multi-core programming, an on-chip hardware debug mechanism for various hardware IPs, and a two-way cross trigger mechanism to synchronize the debug processes of software and hardware. Experimental results on a FPGA prototyping board demonstrate the effectiveness and efficiency of this platform in identifying the root causes of failures for multiple-core SOC systems with multiple-clock domains.

Original languageEnglish
Title of host publicationProceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011
Pages259-262
Number of pages4
DOIs
Publication statusPublished - 2011 Dec 1
Event2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen, China
Duration: 2011 Oct 252011 Oct 28

Publication series

NameProceedings of International Conference on ASIC
ISSN (Print)2162-7541
ISSN (Electronic)2162-755X

Other

Other2011 IEEE 9th International Conference on ASIC, ASICON 2011
Country/TerritoryChina
CityXiamen
Period11-10-2511-10-28

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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