A speed-improved architecture for CMOS programmable divider

Ching Wen Hsu; Yu Sheng Lin; Chun Lin Lu; Yeong Her Wang; Kuo Sheng Cheng

doi:10.1109/ICICIC.2009.54

A speed-improved architecture for CMOS programmable divider

Ching Wen Hsu, Yu Sheng Lin, Chun Lin Lu, Yeong Her Wang, Kuo Sheng Cheng

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper proposes a novel dynamic logic which not only has a lower output parasitic capacitance but also has a switchable characteristic to achieve the speed improvement in the application of programmable divider. The speed of some logic circuits is discussed in this paper. A 16-GHz divide-bytwo frequency divider based on the proposed dynamic logic has been demonstrated in TSMC 0.13-μm CMOS process, too. After a successful simulation, the implemented frequency divider has an operating range from 10.5 to 16.5 GHz and a maximum input sensitivity of 5 mV in amplitude at 13.5 GHz under a supply voltage of 1.3 V and a core power consumption of 4.7 mW.

Original language	English
Title of host publication	2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009
Pages	585-588
Number of pages	4
DOIs	https://doi.org/10.1109/ICICIC.2009.54
Publication status	Published - 2009 Dec 1
Event	2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009 - Kaohsiung, Taiwan Duration: 2009 Dec 7 → 2009 Dec 9

Publication series

Name	2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009

Other

Other	2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009
Country/Territory	Taiwan
City	Kaohsiung
Period	09-12-07 → 09-12-09

All Science Journal Classification (ASJC) codes

Computational Theory and Mathematics
Computer Networks and Communications
Software

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10.1109/ICICIC.2009.54

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Hsu, C. W., Lin, Y. S., Lu, C. L., Wang, Y. H., & Cheng, K. S. (2009). A speed-improved architecture for CMOS programmable divider. In 2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009 (pp. 585-588). Article 5412507 (2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009). https://doi.org/10.1109/ICICIC.2009.54

@inproceedings{9aa3b8207bc14ba99fbcb298d328e698,

title = "A speed-improved architecture for CMOS programmable divider",

abstract = "This paper proposes a novel dynamic logic which not only has a lower output parasitic capacitance but also has a switchable characteristic to achieve the speed improvement in the application of programmable divider. The speed of some logic circuits is discussed in this paper. A 16-GHz divide-bytwo frequency divider based on the proposed dynamic logic has been demonstrated in TSMC 0.13-μm CMOS process, too. After a successful simulation, the implemented frequency divider has an operating range from 10.5 to 16.5 GHz and a maximum input sensitivity of 5 mV in amplitude at 13.5 GHz under a supply voltage of 1.3 V and a core power consumption of 4.7 mW.",

author = "Hsu, {Ching Wen} and Lin, {Yu Sheng} and Lu, {Chun Lin} and Wang, {Yeong Her} and Cheng, {Kuo Sheng}",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/ICICIC.2009.54",

language = "English",

isbn = "9780769538730",

series = "2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009",

pages = "585--588",

booktitle = "2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009",

note = "2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009 ; Conference date: 07-12-2009 Through 09-12-2009",

}

Hsu, CW, Lin, YS, Lu, CL, Wang, YH & Cheng, KS 2009, A speed-improved architecture for CMOS programmable divider. in 2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009., 5412507, 2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009, pp. 585-588, 2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009, Kaohsiung, Taiwan, 09-12-07. https://doi.org/10.1109/ICICIC.2009.54

A speed-improved architecture for CMOS programmable divider. / Hsu, Ching Wen; Lin, Yu Sheng; Lu, Chun Lin et al.
2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009. 2009. p. 585-588 5412507 (2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A speed-improved architecture for CMOS programmable divider

AU - Hsu, Ching Wen

AU - Lin, Yu Sheng

AU - Lu, Chun Lin

AU - Wang, Yeong Her

AU - Cheng, Kuo Sheng

PY - 2009/12/1

Y1 - 2009/12/1

N2 - This paper proposes a novel dynamic logic which not only has a lower output parasitic capacitance but also has a switchable characteristic to achieve the speed improvement in the application of programmable divider. The speed of some logic circuits is discussed in this paper. A 16-GHz divide-bytwo frequency divider based on the proposed dynamic logic has been demonstrated in TSMC 0.13-μm CMOS process, too. After a successful simulation, the implemented frequency divider has an operating range from 10.5 to 16.5 GHz and a maximum input sensitivity of 5 mV in amplitude at 13.5 GHz under a supply voltage of 1.3 V and a core power consumption of 4.7 mW.

AB - This paper proposes a novel dynamic logic which not only has a lower output parasitic capacitance but also has a switchable characteristic to achieve the speed improvement in the application of programmable divider. The speed of some logic circuits is discussed in this paper. A 16-GHz divide-bytwo frequency divider based on the proposed dynamic logic has been demonstrated in TSMC 0.13-μm CMOS process, too. After a successful simulation, the implemented frequency divider has an operating range from 10.5 to 16.5 GHz and a maximum input sensitivity of 5 mV in amplitude at 13.5 GHz under a supply voltage of 1.3 V and a core power consumption of 4.7 mW.

UR - http://www.scopus.com/inward/record.url?scp=77951428699&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77951428699&partnerID=8YFLogxK

U2 - 10.1109/ICICIC.2009.54

DO - 10.1109/ICICIC.2009.54

M3 - Conference contribution

AN - SCOPUS:77951428699

SN - 9780769538730

T3 - 2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009

SP - 585

EP - 588

BT - 2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009

T2 - 2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009

Y2 - 7 December 2009 through 9 December 2009

ER -

A speed-improved architecture for CMOS programmable divider

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