A speed-improved architecture for CMOS programmable divider

Ching Wen Hsu, Yu Sheng Lin, Chun Lin Lu, Yeong Her Wang, Kuo Sheng Cheng

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper proposes a novel dynamic logic which not only has a lower output parasitic capacitance but also has a switchable characteristic to achieve the speed improvement in the application of programmable divider. The speed of some logic circuits is discussed in this paper. A 16-GHz divide-bytwo frequency divider based on the proposed dynamic logic has been demonstrated in TSMC 0.13-μm CMOS process, too. After a successful simulation, the implemented frequency divider has an operating range from 10.5 to 16.5 GHz and a maximum input sensitivity of 5 mV in amplitude at 13.5 GHz under a supply voltage of 1.3 V and a core power consumption of 4.7 mW.

Original languageEnglish
Title of host publication2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009
Pages585-588
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009 - Kaohsiung, Taiwan
Duration: 2009 Dec 72009 Dec 9

Publication series

Name2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009

Other

Other2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009
CountryTaiwan
CityKaohsiung
Period09-12-0709-12-09

Fingerprint

Logic circuits
Electric power utilization
Capacitance
Electric potential

All Science Journal Classification (ASJC) codes

  • Computational Theory and Mathematics
  • Computer Networks and Communications
  • Software

Cite this

Hsu, C. W., Lin, Y. S., Lu, C. L., Wang, Y. H., & Cheng, K. S. (2009). A speed-improved architecture for CMOS programmable divider. In 2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009 (pp. 585-588). [5412507] (2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009). https://doi.org/10.1109/ICICIC.2009.54
Hsu, Ching Wen ; Lin, Yu Sheng ; Lu, Chun Lin ; Wang, Yeong Her ; Cheng, Kuo Sheng. / A speed-improved architecture for CMOS programmable divider. 2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009. 2009. pp. 585-588 (2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009).
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Hsu, CW, Lin, YS, Lu, CL, Wang, YH & Cheng, KS 2009, A speed-improved architecture for CMOS programmable divider. in 2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009., 5412507, 2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009, pp. 585-588, 2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009, Kaohsiung, Taiwan, 09-12-07. https://doi.org/10.1109/ICICIC.2009.54

A speed-improved architecture for CMOS programmable divider. / Hsu, Ching Wen; Lin, Yu Sheng; Lu, Chun Lin; Wang, Yeong Her; Cheng, Kuo Sheng.

2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009. 2009. p. 585-588 5412507 (2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - This paper proposes a novel dynamic logic which not only has a lower output parasitic capacitance but also has a switchable characteristic to achieve the speed improvement in the application of programmable divider. The speed of some logic circuits is discussed in this paper. A 16-GHz divide-bytwo frequency divider based on the proposed dynamic logic has been demonstrated in TSMC 0.13-μm CMOS process, too. After a successful simulation, the implemented frequency divider has an operating range from 10.5 to 16.5 GHz and a maximum input sensitivity of 5 mV in amplitude at 13.5 GHz under a supply voltage of 1.3 V and a core power consumption of 4.7 mW.

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Hsu CW, Lin YS, Lu CL, Wang YH, Cheng KS. A speed-improved architecture for CMOS programmable divider. In 2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009. 2009. p. 585-588. 5412507. (2009 4th International Conference on Innovative Computing, Information and Control, ICICIC 2009). https://doi.org/10.1109/ICICIC.2009.54