TY - GEN
T1 - A Stride-Away Programming Scheme to Resolve Crash Recoverability and Data Readability Issues of Multi-Level-Cell Flash Memory
AU - Ho, Chien Chung
AU - Li, Yung Chun
AU - Lin, Ping Hsien
AU - Wang, Wei Chen
AU - Chang, Yuan Hao
N1 - Funding Information:
This work was supported in part by the Ministry of Science and Technology under grant nos. 106-2218-E-194-012-MY3, 105-2221-E-001-013-MY3, 105-2221-E-001-004-MY2, and 107-3114-E-002-008.
Funding Information:
This work was supported in part by the Ministry of Science and Technology under grant nos. 106-2218-E-194 -012 -MY3, 105-2221-E-001-013-MY3, 105-2221-E-001-004-MY2, and 107-3114-E-002-008.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/11/15
Y1 - 2018/11/15
N2 - The multi-level-cell (MLC) technique is widely adopted by flash memory vendors to increase the chip capacity and to lower the cost, but also results in serious reliability problems. To improve the reliability of MLC flash memory, conventional MLC programming approaches tend to adopt the incremental step pulse program (ISPP) procedure and N-shape programming sequence to program the MLC flash cells. These approaches can improve the reliability of MLC flash memory by reducing the effects of programming disturbance; however, it could further result in the crash recoverability and data readability issues. To ensure the crash recoverability, the backup procedure is necessary for supporting the sudden-power-off-recovery function, and it is typically adopted to avoid data corruption before programming TLC flash pages. Such a backup procedure would further result in the bad programming performance. This motivates this work to explore the innovative programming design for resolving crash recoverability and data readability issues of multi-level-cell flash memory. Thus, to eliminate the negative effects caused by the conventional programming methods, this paper presents and realizes a stride-away MLC programming scheme. The proposed stride-away programming scheme could resolve both the crash recoverability and the data readability issues without the adoption of backup procedures. As a result, the programming performance can also be improved with the proposed stride-away programming scheme. A series of experiments were conducted to evaluate the capability of the proposed design, for which we prove that the proposed scheme can boost the write performance up to 1.8 times.
AB - The multi-level-cell (MLC) technique is widely adopted by flash memory vendors to increase the chip capacity and to lower the cost, but also results in serious reliability problems. To improve the reliability of MLC flash memory, conventional MLC programming approaches tend to adopt the incremental step pulse program (ISPP) procedure and N-shape programming sequence to program the MLC flash cells. These approaches can improve the reliability of MLC flash memory by reducing the effects of programming disturbance; however, it could further result in the crash recoverability and data readability issues. To ensure the crash recoverability, the backup procedure is necessary for supporting the sudden-power-off-recovery function, and it is typically adopted to avoid data corruption before programming TLC flash pages. Such a backup procedure would further result in the bad programming performance. This motivates this work to explore the innovative programming design for resolving crash recoverability and data readability issues of multi-level-cell flash memory. Thus, to eliminate the negative effects caused by the conventional programming methods, this paper presents and realizes a stride-away MLC programming scheme. The proposed stride-away programming scheme could resolve both the crash recoverability and the data readability issues without the adoption of backup procedures. As a result, the programming performance can also be improved with the proposed stride-away programming scheme. A series of experiments were conducted to evaluate the capability of the proposed design, for which we prove that the proposed scheme can boost the write performance up to 1.8 times.
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U2 - 10.1109/NVMSA.2018.00019
DO - 10.1109/NVMSA.2018.00019
M3 - Conference contribution
AN - SCOPUS:85059818856
T3 - Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018
SP - 67
EP - 72
BT - Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018
Y2 - 28 August 2018 through 31 August 2018
ER -