A sub-200-mV voltage-scalable SRAM with tolerance of access failure by self-activated bitline sensing

Shien Chun Luo; Lih Yih Chiou

doi:10.1109/TCSII.2010.2048360

A sub-200-mV voltage-scalable SRAM with tolerance of access failure by self-activated bitline sensing

Shien Chun Luo, Lih Yih Chiou

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

14 Citations (Scopus)

Abstract

The access timing control of low-voltage static random access memory cells encounters crucial challenges in the presence of within-die (WID) variations, which induce severe delay mismatches between the timing-reference circuit and the bitlines. Prevention of early activation of sense amplifiers (SAs) is thus required to improve the yield. This brief proposes a novel SA-activation scheme by sensing differential bitlines locally and concurrently. The proposed structure effectively tolerates the WID variations and supports dynamic voltage scaling down to the subthreshold supply voltage. Measurement results show that the fabricated 8-kb test chips using 90-nm technology can be operated at the supply voltage range from 1 V (nominal V_dd) to 0.16 V. The maximum operating frequency at 0.16 V is up to 200 kHz.

Original language	English
Article number	5471175
Pages (from-to)	440-445
Number of pages	6
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	57
Issue number	6
DOIs	https://doi.org/10.1109/TCSII.2010.2048360
Publication status	Published - 2010 Jun

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/TCSII.2010.2048360

Cite this

@article{8d1119e9ad7a4e1cb151827c59ada36f,

title = "A sub-200-mV voltage-scalable SRAM with tolerance of access failure by self-activated bitline sensing",

abstract = "The access timing control of low-voltage static random access memory cells encounters crucial challenges in the presence of within-die (WID) variations, which induce severe delay mismatches between the timing-reference circuit and the bitlines. Prevention of early activation of sense amplifiers (SAs) is thus required to improve the yield. This brief proposes a novel SA-activation scheme by sensing differential bitlines locally and concurrently. The proposed structure effectively tolerates the WID variations and supports dynamic voltage scaling down to the subthreshold supply voltage. Measurement results show that the fabricated 8-kb test chips using 90-nm technology can be operated at the supply voltage range from 1 V (nominal Vdd) to 0.16 V. The maximum operating frequency at 0.16 V is up to 200 kHz.",

author = "Luo, {Shien Chun} and Chiou, {Lih Yih}",

note = "Funding Information: Manuscript received September 10, 2009; revised December 24, 2009; accepted February 10, 2010. Date of publication May 24, 2010; date of current version June 16, 2010. This work was supported by the National Science Council, Taiwan, under Grant NSC 98-2220-E-006-006. This paper was recommended by Associate Editor M. Anis.",

year = "2010",

month = jun,

doi = "10.1109/TCSII.2010.2048360",

language = "English",

volume = "57",

pages = "440--445",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-7747",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "6",

}

TY - JOUR

T1 - A sub-200-mV voltage-scalable SRAM with tolerance of access failure by self-activated bitline sensing

AU - Luo, Shien Chun

AU - Chiou, Lih Yih

N1 - Funding Information: Manuscript received September 10, 2009; revised December 24, 2009; accepted February 10, 2010. Date of publication May 24, 2010; date of current version June 16, 2010. This work was supported by the National Science Council, Taiwan, under Grant NSC 98-2220-E-006-006. This paper was recommended by Associate Editor M. Anis.

PY - 2010/6

Y1 - 2010/6

N2 - The access timing control of low-voltage static random access memory cells encounters crucial challenges in the presence of within-die (WID) variations, which induce severe delay mismatches between the timing-reference circuit and the bitlines. Prevention of early activation of sense amplifiers (SAs) is thus required to improve the yield. This brief proposes a novel SA-activation scheme by sensing differential bitlines locally and concurrently. The proposed structure effectively tolerates the WID variations and supports dynamic voltage scaling down to the subthreshold supply voltage. Measurement results show that the fabricated 8-kb test chips using 90-nm technology can be operated at the supply voltage range from 1 V (nominal Vdd) to 0.16 V. The maximum operating frequency at 0.16 V is up to 200 kHz.

AB - The access timing control of low-voltage static random access memory cells encounters crucial challenges in the presence of within-die (WID) variations, which induce severe delay mismatches between the timing-reference circuit and the bitlines. Prevention of early activation of sense amplifiers (SAs) is thus required to improve the yield. This brief proposes a novel SA-activation scheme by sensing differential bitlines locally and concurrently. The proposed structure effectively tolerates the WID variations and supports dynamic voltage scaling down to the subthreshold supply voltage. Measurement results show that the fabricated 8-kb test chips using 90-nm technology can be operated at the supply voltage range from 1 V (nominal Vdd) to 0.16 V. The maximum operating frequency at 0.16 V is up to 200 kHz.

UR - http://www.scopus.com/inward/record.url?scp=77953723692&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77953723692&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2010.2048360

DO - 10.1109/TCSII.2010.2048360

M3 - Article

AN - SCOPUS:77953723692

SN - 1549-7747

VL - 57

SP - 440

EP - 445

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

IS - 6

M1 - 5471175

ER -

A sub-200-mV voltage-scalable SRAM with tolerance of access failure by self-activated bitline sensing

Abstract

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this