A sub-200-mV voltage-scalable SRAM with tolerance of access failure by self-activated bitline sensing

Shien Chun Luo, Lih Yih Chiou

Research output: Contribution to journalArticlepeer-review

12 Citations (Scopus)

Abstract

The access timing control of low-voltage static random access memory cells encounters crucial challenges in the presence of within-die (WID) variations, which induce severe delay mismatches between the timing-reference circuit and the bitlines. Prevention of early activation of sense amplifiers (SAs) is thus required to improve the yield. This brief proposes a novel SA-activation scheme by sensing differential bitlines locally and concurrently. The proposed structure effectively tolerates the WID variations and supports dynamic voltage scaling down to the subthreshold supply voltage. Measurement results show that the fabricated 8-kb test chips using 90-nm technology can be operated at the supply voltage range from 1 V (nominal Vdd) to 0.16 V. The maximum operating frequency at 0.16 V is up to 200 kHz.

Original languageEnglish
Article number5471175
Pages (from-to)440-445
Number of pages6
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume57
Issue number6
DOIs
Publication statusPublished - 2010 Jun 1

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A sub-200-mV voltage-scalable SRAM with tolerance of access failure by self-activated bitline sensing'. Together they form a unique fingerprint.

Cite this