A subthreshold SRAM cell with autonomous bitline-voltage clamping

Shien Chun Luo, Lih Yih Chiou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Ultra-low power SRAM is a promising memory for the next-generation electronics that focus on green and power-aware computing. Unfortunately, ultra-low power SRAM encounters serious timing uncertainty. One of the major problems is that the conventional voltage-clamping circuits cannot work when the bitlines have serious with-in-die variations. The full swing, usually required on the bitline, causes unwanted power dispassion. Therefore, this work proposes a novel SRAM cell that can clamp the bitline voltage autonomously. This voltage clamping is also independent in each bitline and is adapted automatically under dynamic voltage scaling. The dynamic power on bitline discharge can be saved by 75% by using the proposed structure, with an acceptable overhead in access time.

Original languageEnglish
Title of host publication2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
Pages150-153
Number of pages4
DOIs
Publication statusPublished - 2010 Dec 1
Event2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Kaohsiung, Taiwan
Duration: 2010 Nov 182010 Nov 19

Publication series

Name2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program

Other

Other2010 International Symposium on Next-Generation Electronics, ISNE 2010
CountryTaiwan
CityKaohsiung
Period10-11-1810-11-19

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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