A successive approximation ADC with resistor-capacitor hybrid structure

Ting Zi Chen, Soon-Jyh Chang, Guan Ying Huang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper presents a 10-bit 50MS/s successive approximation register (SAR) ADC with low input capacitance that uses an on-chip resistive ladder to arrange a new switching scheme. The proposed arrangement not only reduces the total input capacitance, but also performs the predictive capacitor switching sequence to further reduce the power consumption. Therefore, the proposed SAR ADC has the features of small area and low power consumption. Compared to conventional SAR ADCs, the proposed ADC reduces the input capacitance to 512 fF for 10-bit resolution. This work is fabricated in TSMC 90-nm 1P9M CMOS process. This prototype chip consumes 0.703 mW from a 1.2-V supply and the ENOB is 9.3 bits at 50 MS/s sampling rate. The resultant FoM is 28 fJ/conversion-step.

Original languageEnglish
Title of host publication2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
DOIs
Publication statusPublished - 2013 Aug 15
Event2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 - Hsinchu, Taiwan
Duration: 2013 Apr 222013 Apr 24

Publication series

Name2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

Other

Other2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
CountryTaiwan
CityHsinchu
Period13-04-2213-04-24

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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