A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling

Tsung Chu Huang; Jing Chi Tzeng; Yuan Wei Chao; Ji Jan Chen; Wei Ting Liu; Kuen Jong Lee

doi:10.1109/VDAT.2006.258151

A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling

Tsung Chu Huang, Jing Chi Tzeng, Yuan Wei Chao, Ji Jan Chen, Wei Ting Liu, Kuen Jong Lee

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Original language	English
Title of host publication	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
Pages	167-170
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2006.258151
Publication status	Published - 2007
Event	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu, Taiwan Duration: 2007 Apr 26 → 2007 Apr 28

Publication series

Name	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Other

Other	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
Country/Territory	Taiwan
City	Hsinchu
Period	07-04-26 → 07-04-28

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/VDAT.2006.258151

Cite this

Huang, T. C., Tzeng, J. C., Chao, Y. W., Chen, J. J., Liu, W. T., & Lee, K. J. (2007). A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers (pp. 167-170). [4027523] (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2006.258151

Huang, Tsung Chu ; Tzeng, Jing Chi ; Chao, Yuan Wei et al. / A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling. 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. pp. 167-170 (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers).

@inproceedings{98bb89663dc64d6493c48b65d4bee384,

title = "A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling",

author = "Huang, {Tsung Chu} and Tzeng, {Jing Chi} and Chao, {Yuan Wei} and Chen, {Ji Jan} and Liu, {Wei Ting} and Lee, {Kuen Jong}",

year = "2007",

doi = "10.1109/VDAT.2006.258151",

language = "English",

isbn = "1424401798",

series = "2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers",

pages = "167--170",

booktitle = "2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers",

note = "2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 ; Conference date: 26-04-2007 Through 28-04-2007",

}

Huang, TC, Tzeng, JC, Chao, YW, Chen, JJ, Liu, WT & Lee, KJ 2007, A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling. in 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers., 4027523, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers, pp. 167-170, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006, Hsinchu, Taiwan, 07-04-26. https://doi.org/10.1109/VDAT.2006.258151

A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling. / Huang, Tsung Chu; Tzeng, Jing Chi; Chao, Yuan Wei et al.

2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 167-170 4027523 (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling

AU - Huang, Tsung Chu

AU - Tzeng, Jing Chi

AU - Chao, Yuan Wei

AU - Chen, Ji Jan

AU - Liu, Wei Ting

AU - Lee, Kuen Jong

PY - 2007

Y1 - 2007

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UR - http://www.scopus.com/inward/citedby.url?scp=34748911725&partnerID=8YFLogxK

U2 - 10.1109/VDAT.2006.258151

DO - 10.1109/VDAT.2006.258151

M3 - Conference contribution

AN - SCOPUS:34748911725

SN - 1424401798

SN - 9781424401796

T3 - 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

SP - 167

EP - 170

BT - 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

T2 - 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006

Y2 - 26 April 2007 through 28 April 2007

ER -

Huang TC, Tzeng JC, Chao YW, Chen JJ, Liu WT, Lee KJ. A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 167-170. 4027523. (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2006.258151

A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling

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Other

All Science Journal Classification (ASJC) codes

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