This article presents the control circuit of a power converter that regulates the computing speed of a digital circuit. The proposed circuit implements a digital delay regulation of a digital delay line (DDL) matched with the ring oscillator (RO) that clocks the digital subsystem. The converter regulates the supply voltage of the digital subsystem so that the propagation delay through the DDL matches a time reference. Consequently, the frequency of the RO tracks the DDL delay and the frequency keeps a controlled value over process, voltage, and temperature (PVT). A 65-nm CMOS prototype validates the proposed method. The prototype includes an Arm Cortex-M33 CPU and memories optimized for sub-threshold operation. With the proposed method, the computing performance of the CPU is guaranteed for running real-time application while minimizing the supply voltage margins.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering