TY - JOUR
T1 - A Supply Voltage Control Method for Performance Guaranteed Ultra-Low-Power Microcontroller
AU - Labbé, Benoît
AU - Fan, Philex
AU - Achuthan, Thanusree
AU - Prabhat, Pranay
AU - Knight, Graham Peter
AU - Myers, James
N1 - Funding Information:
Manuscript received May 29, 2020; revised August 18, 2020; accepted September 5, 2020. Date of publication September 22, 2020; date of current version January 28, 2021. This article was approved by Associate Editor Vivek De. This work was supported by the Defense Advanced Research Projects Agency (DARPA). The views, opinions, and/or findings expressed are those of the author(s) and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government. (Corresponding author: Benoît Labbé.) The authors are with Arm Ltd., Cambridge CB1 9NJ, U.K (e-mail: [email protected]).
Publisher Copyright:
© 1966-2012 IEEE.
PY - 2021/2
Y1 - 2021/2
N2 - This article presents the control circuit of a power converter that regulates the computing speed of a digital circuit. The proposed circuit implements a digital delay regulation of a digital delay line (DDL) matched with the ring oscillator (RO) that clocks the digital subsystem. The converter regulates the supply voltage of the digital subsystem so that the propagation delay through the DDL matches a time reference. Consequently, the frequency of the RO tracks the DDL delay and the frequency keeps a controlled value over process, voltage, and temperature (PVT). A 65-nm CMOS prototype validates the proposed method. The prototype includes an Arm Cortex-M33 CPU and memories optimized for sub-threshold operation. With the proposed method, the computing performance of the CPU is guaranteed for running real-time application while minimizing the supply voltage margins.
AB - This article presents the control circuit of a power converter that regulates the computing speed of a digital circuit. The proposed circuit implements a digital delay regulation of a digital delay line (DDL) matched with the ring oscillator (RO) that clocks the digital subsystem. The converter regulates the supply voltage of the digital subsystem so that the propagation delay through the DDL matches a time reference. Consequently, the frequency of the RO tracks the DDL delay and the frequency keeps a controlled value over process, voltage, and temperature (PVT). A 65-nm CMOS prototype validates the proposed method. The prototype includes an Arm Cortex-M33 CPU and memories optimized for sub-threshold operation. With the proposed method, the computing performance of the CPU is guaranteed for running real-time application while minimizing the supply voltage margins.
UR - https://www.scopus.com/pages/publications/85100313988
UR - https://www.scopus.com/pages/publications/85100313988#tab=citedBy
U2 - 10.1109/JSSC.2020.3023001
DO - 10.1109/JSSC.2020.3023001
M3 - Article
AN - SCOPUS:85100313988
SN - 0018-9200
VL - 56
SP - 601
EP - 611
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 2
M1 - 9203864
ER -