Semiconductor memory testing has been a key problem in testing integrated circuits for years. With their growing density and capacity, the test time grows rapidly if the test methodologies and equipments remain the same. Test time reduction other than parallel insertion - which is expensive and more and more difficult to keep up with the memory capacity growth - is a long time research issue, as test cost is directly related to the time each product stays on the tester. In order to solve the test time reduction (TTR) problem, we propose a systematic approach to analyzing and rearranging the test items in the test flow. We propose three test compaction techniques: 1) removing redundant test items, 2) merging existing test patterns, 3) developing efficient new test patterns. The proposed TTR algorithm is shown to effectively reduce the test time of an industrial DRAM product. The TTR tool also can identify the redundant test items, suggest a proper test list, and provide the correlation between the test items. In the industrial case, about 19.5% of the total test time is reduced, on top of the original manually compacted test flow.