A Systematic Design Methodology of Asynchronous SAR ADCs

Chun Po Huang, Jai-Ming Lin, Ya Ting Shyu, Soon-Jyh Chang

Research output: Contribution to journalArticlepeer-review

15 Citations (Scopus)


Successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used in biomedical and portable/wearable electronic systems due to their excellent power efficiency. However, both the design and the optimization of high-performance SAR ADCs are time consuming, even for well-experienced circuit designers. For system designers, it is also hard to quickly evaluate the feasibility of a given specification in a process node. This paper presents a systematic sizing procedure for asynchronous SAR ADCs based on design considerations. A sizing tool based on the proposed design procedure is also implemented, the sizing results of which are highly competitive in comparison with other state-of-the-art manual works. Moreover, the sizing time is relatively short due to the efficient and effective search algorithms employed. In addition to the simulation results, two silicon proofs with different specifications and process nodes are provided to demonstrate the feasibility of this design methodology.

Original languageEnglish
Article number7332786
Pages (from-to)1835-1848
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number5
Publication statusPublished - 2016 May 1

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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