A systematic methodology to employ error-tolerance for yield improvement

Tong Yu Hsieh, Kuen Jong Lee, Chia Lin Lu, Melvin A. Breuer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Error-tolerance is an innovative concept that can significantly improve the yield of integrated circuits (IC's) by identifying defective yet acceptable chips. A systematic method to employ this concept, however, has not been addressed. In this paper, we propose a general methodology to systematically utilize error-tolerance for practical applications. The proposed methodology explores the error-tolerance features of target designs, evaluates the acceptability of defective chips, and predicts the yield improvement that can be achieved. To illustrate and validate the proposed methodology, we employ a discrete cosine transform (DCT) circuit that has been widely used in multimedia compression systems in a case study. By applying the proposed methodology to the DCT, an error-tolerant design flow is established. Proper attributes are determined for acceptability evaluation, and corresponding test methods are developed to identify acceptable chips. Experimental results show that one can easily specify various acceptability thresholds of the identified error-tolerable attributes to obtain different degrees of yield improvement, which validates the efficiency and effectiveness of the proposed methodology.

Original languageEnglish
Title of host publication2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
Pages105-108
Number of pages4
DOIs
Publication statusPublished - 2008 Sep 5
Event2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT - Hsinchu, Taiwan
Duration: 2008 Apr 232008 Apr 25

Publication series

Name2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Other

Other2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
CountryTaiwan
CityHsinchu
Period08-04-2308-04-25

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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