A test integration methodology for 3D integrated circuits

Che Wei Chou, Jin Fu Li, Ji Jan Chen, Ding Ming Kwai, Yung Fa Chou, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

27 Citations (Scopus)

Abstract

The three-dimensional (3D) integration technology using through silicon via (TSV) provides many benefits over the 2D integration technology. Although many different manufacturing technologies for 3D integrated circuits (ICs) have been presented, some challenges should be overcome before the volume production of 3D ICs. One of the challenges is the testing of 3D ICs. This paper proposes test integration interfaces for controlling the design-for-test circuits in the dies of a 3D IC. The test integration interfaces can support the pre-bond, known-good stack, and post-bond tests. The minimum number of required test pads of the proposed test interface for pre-bond test using is only four. Furthermore, the test interface is compatible with the IEEE 1149.1 standard for the board-level testing. Simulation results show that the area overhead of the proposed test interfaces for a 3D IC with two dies in which each die implements the function of ITC'99 b19 benchmark is only about 0.15%.

Original languageEnglish
Title of host publicationProceedings - 2010 19th IEEE Asian Test Symposium, ATS 2010
Pages377-382
Number of pages6
DOIs
Publication statusPublished - 2010 Dec 1
Event2010 19th IEEE Asian Test Symposium, ATS 2010 - Shanghai, China
Duration: 2010 Dec 12010 Dec 4

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Other

Other2010 19th IEEE Asian Test Symposium, ATS 2010
CountryChina
CityShanghai
Period10-12-0110-12-04

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A test integration methodology for 3D integrated circuits'. Together they form a unique fingerprint.

Cite this