A test-per-clock LFSR reseeding algorithm for concurrent reduction on test sequence length and test data volume

Wei Cheng Lien, Kuen-Jong Lee, Tong Yu Hsieh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

This paper proposes a new test-per-clock BIST method that attempts to minimize the test sequence length and the test data volume simultaneously. An efficient LFSR reseeding algorithm is developed by which each determined seed together with its derived patterns can detect the maximum number of so far undetected faults. During the seed determination process an adaptive X-filling process is first employed to generate a set of candidate patterns for pattern embedding. The process then derives a seed solution that can embed multiple candidate patterns at one time so as to minimize the number of seeds. To shorten the test sequence, the pattern embedding process begins with a small initial set of pseudo-random patterns and will incrementally add more patterns only when necessary. Experimental results show that compared with the previous test-per-clock techniques based on the LFSR- and twisted-ring-counter-reseeding methods, our method can reduce the test sequence length by over 60% with generally smaller numbers of storage bits. When compared with the mapping-logic-based BIST methods, our method can reduce the test sequence length by over 50% with a comparable area overhead.

Original languageEnglish
Title of host publicationProceedings - 2012 IEEE 21st Asian Test Symposium, ATS 2012
Pages278-283
Number of pages6
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 IEEE 21st Asian Test Symposium, ATS 2012 - Niigatta, Japan
Duration: 2012 Nov 192012 Nov 22

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735

Other

Other2012 IEEE 21st Asian Test Symposium, ATS 2012
CountryJapan
CityNiigatta
Period12-11-1912-11-22

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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