TY - GEN

T1 - A test-per-clock LFSR reseeding algorithm for concurrent reduction on test sequence length and test data volume

AU - Lien, Wei Cheng

AU - Lee, Kuen-Jong

AU - Hsieh, Tong Yu

PY - 2012/12/1

Y1 - 2012/12/1

N2 - This paper proposes a new test-per-clock BIST method that attempts to minimize the test sequence length and the test data volume simultaneously. An efficient LFSR reseeding algorithm is developed by which each determined seed together with its derived patterns can detect the maximum number of so far undetected faults. During the seed determination process an adaptive X-filling process is first employed to generate a set of candidate patterns for pattern embedding. The process then derives a seed solution that can embed multiple candidate patterns at one time so as to minimize the number of seeds. To shorten the test sequence, the pattern embedding process begins with a small initial set of pseudo-random patterns and will incrementally add more patterns only when necessary. Experimental results show that compared with the previous test-per-clock techniques based on the LFSR- and twisted-ring-counter-reseeding methods, our method can reduce the test sequence length by over 60% with generally smaller numbers of storage bits. When compared with the mapping-logic-based BIST methods, our method can reduce the test sequence length by over 50% with a comparable area overhead.

AB - This paper proposes a new test-per-clock BIST method that attempts to minimize the test sequence length and the test data volume simultaneously. An efficient LFSR reseeding algorithm is developed by which each determined seed together with its derived patterns can detect the maximum number of so far undetected faults. During the seed determination process an adaptive X-filling process is first employed to generate a set of candidate patterns for pattern embedding. The process then derives a seed solution that can embed multiple candidate patterns at one time so as to minimize the number of seeds. To shorten the test sequence, the pattern embedding process begins with a small initial set of pseudo-random patterns and will incrementally add more patterns only when necessary. Experimental results show that compared with the previous test-per-clock techniques based on the LFSR- and twisted-ring-counter-reseeding methods, our method can reduce the test sequence length by over 60% with generally smaller numbers of storage bits. When compared with the mapping-logic-based BIST methods, our method can reduce the test sequence length by over 50% with a comparable area overhead.

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U2 - 10.1109/ATS.2012.11

DO - 10.1109/ATS.2012.11

M3 - Conference contribution

AN - SCOPUS:84872572789

SN - 9780769548760

T3 - Proceedings of the Asian Test Symposium

SP - 278

EP - 283

BT - Proceedings - 2012 IEEE 21st Asian Test Symposium, ATS 2012

T2 - 2012 IEEE 21st Asian Test Symposium, ATS 2012

Y2 - 19 November 2012 through 22 November 2012

ER -