A Test-per-cycle BIST architecture with low area overhead and no storage requirement

Chung Min Shiao, Wei Cheng Lien, Kuen-Jong Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Test-per-clock BIST scheme has the advantages of very short test application time and small test data volume. However, conventionally this scheme needs an extra parallel response monitor for response analysis that may lead to large area overhead. This paper presents a new test-per-clock BIST method that can perform both pattern generation and response compression concurrently in the same LFSR-based design so as to reduce the area overhead. Furthermore, some internal nets are employed in two ways during test application to help reduce test time and test data volume: 1) as the observation points to enhance fault detectability and 2) as the test data provider for reseeding the LFSR. These two ways lead to the benefits that all required patterns can be generated on chip and at-speed testing can be carried out without using any external or internal storage device. Experimental results show that the presented method can achieve 100% fault coverage in very short time for large ISCAS (IWLS) benchmark circuits using 0.09% (0.03%) of internal nets with 9.29% (8.26%) extra area overhead respectively. When compared with a conventional scan-based design, the area overhead is small considering the features of test-per-clock and no requirement of data storage or expensive test equipment.

Original languageEnglish
Title of host publication2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467394987
DOIs
Publication statusPublished - 2016 May 31
Event2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan
Duration: 2016 Apr 252016 Apr 27

Publication series

Name2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Other

Other2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
CountryTaiwan
CityHsinchu
Period16-04-2516-04-27

Fingerprint

Built-in self test
Clocks
requirements
cycles
clocks
Data storage equipment
Networks (circuits)
Testing
data storage
test equipment
monitors
chips

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Instrumentation

Cite this

Shiao, C. M., Lien, W. C., & Lee, K-J. (2016). A Test-per-cycle BIST architecture with low area overhead and no storage requirement. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 [7482556] (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2016.7482556
Shiao, Chung Min ; Lien, Wei Cheng ; Lee, Kuen-Jong. / A Test-per-cycle BIST architecture with low area overhead and no storage requirement. 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).
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abstract = "Test-per-clock BIST scheme has the advantages of very short test application time and small test data volume. However, conventionally this scheme needs an extra parallel response monitor for response analysis that may lead to large area overhead. This paper presents a new test-per-clock BIST method that can perform both pattern generation and response compression concurrently in the same LFSR-based design so as to reduce the area overhead. Furthermore, some internal nets are employed in two ways during test application to help reduce test time and test data volume: 1) as the observation points to enhance fault detectability and 2) as the test data provider for reseeding the LFSR. These two ways lead to the benefits that all required patterns can be generated on chip and at-speed testing can be carried out without using any external or internal storage device. Experimental results show that the presented method can achieve 100{\%} fault coverage in very short time for large ISCAS (IWLS) benchmark circuits using 0.09{\%} (0.03{\%}) of internal nets with 9.29{\%} (8.26{\%}) extra area overhead respectively. When compared with a conventional scan-based design, the area overhead is small considering the features of test-per-clock and no requirement of data storage or expensive test equipment.",
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Shiao, CM, Lien, WC & Lee, K-J 2016, A Test-per-cycle BIST architecture with low area overhead and no storage requirement. in 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016., 7482556, 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Institute of Electrical and Electronics Engineers Inc., 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, Hsinchu, Taiwan, 16-04-25. https://doi.org/10.1109/VLSI-DAT.2016.7482556

A Test-per-cycle BIST architecture with low area overhead and no storage requirement. / Shiao, Chung Min; Lien, Wei Cheng; Lee, Kuen-Jong.

2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7482556 (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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M3 - Conference contribution

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Shiao CM, Lien WC, Lee K-J. A Test-per-cycle BIST architecture with low area overhead and no storage requirement. In 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7482556. (2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016). https://doi.org/10.1109/VLSI-DAT.2016.7482556