Abstract
A sophisticated SoC chip that incorporates many design modules including 2 ARM-like CPUs, a dynamic voltage and frequency scaling (DVFS) design, a master/slave temperature sensing system, and an on-chip test/debug platform is developed and implemented with TSMC 90 nm technology. Measurement results validate the functions and efficiencies of the whole chip.
| Original language | English |
|---|---|
| Title of host publication | 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 17-18 |
| Number of pages | 2 |
| ISBN (Electronic) | 9781467395694 |
| DOIs | |
| Publication status | Published - 2016 Mar 7 |
| Event | 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 - Macao, Macao Duration: 2016 Jan 25 → 2016 Jan 28 |
Publication series
| Name | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC |
|---|---|
| Volume | 25-28-January-2016 |
Other
| Other | 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 |
|---|---|
| Country | Macao |
| City | Macao |
| Period | 16-01-25 → 16-01-28 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Computer Science Applications
- Computer Graphics and Computer-Aided Design
Cite this
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A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. / Lu, Liang Ying; Chang, Ching Yao; Chen, Zhao Hong; Yeh, Bo Ting; Lu, Tai Hua; Chen, Peng Yu; Tang, Pin Hao; Lee, Kuen Jong; Chiou, Lih Yih; Chang, Soon Jyh; Tsai, Chien Hung; Chen, Chung Ho; Lin, Jai Ming.
2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 17-18 7427980 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 25-28-January-2016).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling
AU - Lu, Liang Ying
AU - Chang, Ching Yao
AU - Chen, Zhao Hong
AU - Yeh, Bo Ting
AU - Lu, Tai Hua
AU - Chen, Peng Yu
AU - Tang, Pin Hao
AU - Lee, Kuen Jong
AU - Chiou, Lih Yih
AU - Chang, Soon Jyh
AU - Tsai, Chien Hung
AU - Chen, Chung Ho
AU - Lin, Jai Ming
PY - 2016/3/7
Y1 - 2016/3/7
N2 - A sophisticated SoC chip that incorporates many design modules including 2 ARM-like CPUs, a dynamic voltage and frequency scaling (DVFS) design, a master/slave temperature sensing system, and an on-chip test/debug platform is developed and implemented with TSMC 90 nm technology. Measurement results validate the functions and efficiencies of the whole chip.
AB - A sophisticated SoC chip that incorporates many design modules including 2 ARM-like CPUs, a dynamic voltage and frequency scaling (DVFS) design, a master/slave temperature sensing system, and an on-chip test/debug platform is developed and implemented with TSMC 90 nm technology. Measurement results validate the functions and efficiencies of the whole chip.
UR - http://www.scopus.com/inward/record.url?scp=84996910356&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84996910356&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2016.7427980
DO - 10.1109/ASPDAC.2016.7427980
M3 - Conference contribution
AN - SCOPUS:84996910356
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 17
EP - 18
BT - 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
PB - Institute of Electrical and Electronics Engineers Inc.
ER -