A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling

Liang Ying Lu, Ching Yao Chang, Zhao Hong Chen, Bo Ting Yeh, Tai Hua Lu, Peng Yu Chen, Pin Hao Tang, Kuen Jong Lee, Lih Yih Chiou, Soon Jyh Chang, Chien Hung Tsai, Chung Ho Chen, Jai Ming Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A sophisticated SoC chip that incorporates many design modules including 2 ARM-like CPUs, a dynamic voltage and frequency scaling (DVFS) design, a master/slave temperature sensing system, and an on-chip test/debug platform is developed and implemented with TSMC 90 nm technology. Measurement results validate the functions and efficiencies of the whole chip.

Original languageEnglish
Title of host publication2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages17-18
Number of pages2
ISBN (Electronic)9781467395694
DOIs
Publication statusPublished - 2016 Mar 7
Event21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 - Macao, Macao
Duration: 2016 Jan 252016 Jan 28

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume25-28-January-2016

Other

Other21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
CountryMacao
CityMacao
Period16-01-2516-01-28

Fingerprint

Program processors
Microprocessor chips
Temperature
Voltage scaling
Dynamic frequency scaling
Hot Temperature
System-on-chip

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Lu, L. Y., Chang, C. Y., Chen, Z. H., Yeh, B. T., Lu, T. H., Chen, P. Y., ... Lin, J. M. (2016). A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. In 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 (pp. 17-18). [7427980] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 25-28-January-2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2016.7427980
Lu, Liang Ying ; Chang, Ching Yao ; Chen, Zhao Hong ; Yeh, Bo Ting ; Lu, Tai Hua ; Chen, Peng Yu ; Tang, Pin Hao ; Lee, Kuen Jong ; Chiou, Lih Yih ; Chang, Soon Jyh ; Tsai, Chien Hung ; Chen, Chung Ho ; Lin, Jai Ming. / A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 17-18 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).
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title = "A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling",
abstract = "A sophisticated SoC chip that incorporates many design modules including 2 ARM-like CPUs, a dynamic voltage and frequency scaling (DVFS) design, a master/slave temperature sensing system, and an on-chip test/debug platform is developed and implemented with TSMC 90 nm technology. Measurement results validate the functions and efficiencies of the whole chip.",
author = "Lu, {Liang Ying} and Chang, {Ching Yao} and Chen, {Zhao Hong} and Yeh, {Bo Ting} and Lu, {Tai Hua} and Chen, {Peng Yu} and Tang, {Pin Hao} and Lee, {Kuen Jong} and Chiou, {Lih Yih} and Chang, {Soon Jyh} and Tsai, {Chien Hung} and Chen, {Chung Ho} and Lin, {Jai Ming}",
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language = "English",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
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Lu, LY, Chang, CY, Chen, ZH, Yeh, BT, Lu, TH, Chen, PY, Tang, PH, Lee, KJ, Chiou, LY, Chang, SJ, Tsai, CH, Chen, CH & Lin, JM 2016, A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. in 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016., 7427980, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 25-28-January-2016, Institute of Electrical and Electronics Engineers Inc., pp. 17-18, 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao, 16-01-25. https://doi.org/10.1109/ASPDAC.2016.7427980

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. / Lu, Liang Ying; Chang, Ching Yao; Chen, Zhao Hong; Yeh, Bo Ting; Lu, Tai Hua; Chen, Peng Yu; Tang, Pin Hao; Lee, Kuen Jong; Chiou, Lih Yih; Chang, Soon Jyh; Tsai, Chien Hung; Chen, Chung Ho; Lin, Jai Ming.

2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 17-18 7427980 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 25-28-January-2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Lu LY, Chang CY, Chen ZH, Yeh BT, Lu TH, Chen PY et al. A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. In 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 17-18. 7427980. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2016.7427980