@inproceedings{3cfe6f257d7e47c6bd9bc0862c4547be,
title = "A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling",
abstract = "A sophisticated SoC chip that incorporates many design modules including 2 ARM-like CPUs, a dynamic voltage and frequency scaling (DVFS) design, a master/slave temperature sensing system, and an on-chip test/debug platform is developed and implemented with TSMC 90 nm technology. Measurement results validate the functions and efficiencies of the whole chip.",
author = "Lu, {Liang Ying} and Chang, {Ching Yao} and Chen, {Zhao Hong} and Yeh, {Bo Ting} and Lu, {Tai Hua} and Chen, {Peng Yu} and Tang, {Pin Hao} and Lee, {Kuen Jong} and Chiou, {Lih Yih} and Chang, {Soon Jyh} and Tsai, {Chien Hung} and Chen, {Chung Ho} and Lin, {Jai Ming}",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE. Copyright: Copyright 2017 Elsevier B.V., All rights reserved.; 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 ; Conference date: 25-01-2016 Through 28-01-2016",
year = "2016",
month = mar,
day = "7",
doi = "10.1109/ASPDAC.2016.7427980",
language = "English",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "17--18",
booktitle = "2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016",
address = "United States",
}