A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling

Liang Ying Lu; Ching Yao Chang; Zhao Hong Chen; Bo Ting Yeh; Tai Hua Lu; Peng Yu Chen; Pin Hao Tang; Kuen Jong Lee; Lih Yih Chiou; Soon Jyh Chang; Chien Hung Tsai; Chung Ho Chen; Jai Ming Lin

doi:10.1109/ASPDAC.2016.7427980

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling

Liang Ying Lu, Ching Yao Chang, Zhao Hong Chen, Bo Ting Yeh, Tai Hua Lu, Peng Yu Chen, Pin Hao Tang, Kuen Jong Lee, Lih Yih Chiou, Soon Jyh Chang, Chien Hung Tsai, Chung Ho Chen, Jai Ming Lin

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

A sophisticated SoC chip that incorporates many design modules including 2 ARM-like CPUs, a dynamic voltage and frequency scaling (DVFS) design, a master/slave temperature sensing system, and an on-chip test/debug platform is developed and implemented with TSMC 90 nm technology. Measurement results validate the functions and efficiencies of the whole chip.

Original language	English
Title of host publication	2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	17-18
Number of pages	2
ISBN (Electronic)	9781467395694
DOIs	https://doi.org/10.1109/ASPDAC.2016.7427980
Publication status	Published - 2016 Mar 7
Event	21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 - Macao, Macao Duration: 2016 Jan 25 → 2016 Jan 28

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	25-28-January-2016

Other

Other	21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
Country/Territory	Macao
City	Macao
Period	16-01-25 → 16-01-28

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Computer Science Applications
Computer Graphics and Computer-Aided Design

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10.1109/ASPDAC.2016.7427980

Cite this

Lu, L. Y., Chang, C. Y., Chen, Z. H., Yeh, B. T., Lu, T. H., Chen, P. Y., Tang, P. H., Lee, K. J., Chiou, L. Y., Chang, S. J., Tsai, C. H., Chen, C. H., & Lin, J. M. (2016). A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. In 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 (pp. 17-18). Article 7427980 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 25-28-January-2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2016.7427980

Lu, Liang Ying ; Chang, Ching Yao ; Chen, Zhao Hong et al. / A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 17-18 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

@inproceedings{3cfe6f257d7e47c6bd9bc0862c4547be,

title = "A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling",

abstract = "A sophisticated SoC chip that incorporates many design modules including 2 ARM-like CPUs, a dynamic voltage and frequency scaling (DVFS) design, a master/slave temperature sensing system, and an on-chip test/debug platform is developed and implemented with TSMC 90 nm technology. Measurement results validate the functions and efficiencies of the whole chip.",

author = "Lu, {Liang Ying} and Chang, {Ching Yao} and Chen, {Zhao Hong} and Yeh, {Bo Ting} and Lu, {Tai Hua} and Chen, {Peng Yu} and Tang, {Pin Hao} and Lee, {Kuen Jong} and Chiou, {Lih Yih} and Chang, {Soon Jyh} and Tsai, {Chien Hung} and Chen, {Chung Ho} and Lin, {Jai Ming}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 ; Conference date: 25-01-2016 Through 28-01-2016",

year = "2016",

month = mar,

day = "7",

doi = "10.1109/ASPDAC.2016.7427980",

language = "English",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "17--18",

booktitle = "2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016",

address = "United States",

}

Lu, LY, Chang, CY, Chen, ZH, Yeh, BT, Lu, TH, Chen, PY, Tang, PH, Lee, KJ , Chiou, LY , Chang, SJ , Tsai, CH , Chen, CH & Lin, JM 2016, A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. in 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016., 7427980, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 25-28-January-2016, Institute of Electrical and Electronics Engineers Inc., pp. 17-18, 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016, Macao, Macao, 16-01-25. https://doi.org/10.1109/ASPDAC.2016.7427980

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. / Lu, Liang Ying; Chang, Ching Yao; Chen, Zhao Hong et al.
2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. p. 17-18 7427980 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 25-28-January-2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Lu, Liang Ying

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AU - Yeh, Bo Ting

AU - Lu, Tai Hua

AU - Chen, Peng Yu

AU - Tang, Pin Hao

AU - Lee, Kuen Jong

AU - Chiou, Lih Yih

AU - Chang, Soon Jyh

AU - Tsai, Chien Hung

AU - Chen, Chung Ho

AU - Lin, Jai Ming

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AB - A sophisticated SoC chip that incorporates many design modules including 2 ARM-like CPUs, a dynamic voltage and frequency scaling (DVFS) design, a master/slave temperature sensing system, and an on-chip test/debug platform is developed and implemented with TSMC 90 nm technology. Measurement results validate the functions and efficiencies of the whole chip.

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Lu LY, Chang CY, Chen ZH, Yeh BT, Lu TH, Chen PY et al. A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. In 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. p. 17-18. 7427980. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1109/ASPDAC.2016.7427980

A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling

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