A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling

Liang Ying Lu, Ching Yao Chang, Zhao Hong Chen, Bo Ting Yeh, Tai Hua Lu, Peng Yu Chen, Pin Hao Tang, Kuen Jong Lee, Lih Yih Chiou, Soon Jyh Chang, Chien Hung Tsai, Chung Ho Chen, Jai Ming Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A sophisticated SoC chip that incorporates many design modules including 2 ARM-like CPUs, a dynamic voltage and frequency scaling (DVFS) design, a master/slave temperature sensing system, and an on-chip test/debug platform is developed and implemented with TSMC 90 nm technology. Measurement results validate the functions and efficiencies of the whole chip.

Original languageEnglish
Title of host publication2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages17-18
Number of pages2
ISBN (Electronic)9781467395694
DOIs
Publication statusPublished - 2016 Mar 7
Event21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 - Macao, Macao
Duration: 2016 Jan 252016 Jan 28

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume25-28-January-2016

Other

Other21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
CountryMacao
CityMacao
Period16-01-2516-01-28

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

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