TY - GEN
T1 - A Top-down, mixed-level design methodology for CT BP ΔΣ modulator using verilog-A
AU - Chu, Hung Yuan
AU - Yang, Chun Hung
AU - Leng, Chi Wai
AU - Tsai, Chien Hung
PY - 2008
Y1 - 2008
N2 - This paper presents a design methodology of a continuous-time (CT) Band-pass (BP) ΔΣ modulator which can improve the design procedure. The proposed top-down, mixed- level design platform is implemented under Cadence's Spectre environment using Verilog-A. A 2nd order CT BP ΔΣ modulator for WCDMA applications. The central frequency of this modulator is at 100MHz and the quantizer operates at 400MHz clock frequency. The modulator is designed using TSMC 0.35μm CMOS technology with a supply voltage of 3.3V. The simulated maximum SNDR is 40dB for a 3.84MHz bandwidth, which corresponds to a resolution of 6 bits.
AB - This paper presents a design methodology of a continuous-time (CT) Band-pass (BP) ΔΣ modulator which can improve the design procedure. The proposed top-down, mixed- level design platform is implemented under Cadence's Spectre environment using Verilog-A. A 2nd order CT BP ΔΣ modulator for WCDMA applications. The central frequency of this modulator is at 100MHz and the quantizer operates at 400MHz clock frequency. The modulator is designed using TSMC 0.35μm CMOS technology with a supply voltage of 3.3V. The simulated maximum SNDR is 40dB for a 3.84MHz bandwidth, which corresponds to a resolution of 6 bits.
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U2 - 10.1109/APCCAS.2008.4746289
DO - 10.1109/APCCAS.2008.4746289
M3 - Conference contribution
AN - SCOPUS:62949189584
SN - 9781424423422
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 1390
EP - 1393
BT - Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
T2 - APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Y2 - 30 November 2008 through 3 December 2008
ER -