A Top-down, mixed-level design methodology for CT BP ΔΣ modulator using verilog-A

Hung Yuan Chu, Chun Hung Yang, Chi Wai Leng, Chien Hung Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper presents a design methodology of a continuous-time (CT) Band-pass (BP) ΔΣ modulator which can improve the design procedure. The proposed top-down, mixed- level design platform is implemented under Cadence's Spectre environment using Verilog-A. A 2nd order CT BP ΔΣ modulator for WCDMA applications. The central frequency of this modulator is at 100MHz and the quantizer operates at 400MHz clock frequency. The modulator is designed using TSMC 0.35μm CMOS technology with a supply voltage of 3.3V. The simulated maximum SNDR is 40dB for a 3.84MHz bandwidth, which corresponds to a resolution of 6 bits.

Original languageEnglish
Title of host publicationProceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Pages1390-1393
Number of pages4
DOIs
Publication statusPublished - 2008
EventAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems - Macao, China
Duration: 2008 Nov 302008 Dec 3

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

OtherAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
CountryChina
CityMacao
Period08-11-3008-12-03

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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