A Top-down, mixed-level design methodology for CT BP ΔΣ modulator using verilog-A

Hung Yuan Chu; Chun Hung Yang; Chi Wai Leng; Chien Hung Tsai

doi:10.1109/APCCAS.2008.4746289

A Top-down, mixed-level design methodology for CT BP ΔΣ modulator using verilog-A

Hung Yuan Chu, Chun Hung Yang, Chi Wai Leng, Chien Hung Tsai

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

This paper presents a design methodology of a continuous-time (CT) Band-pass (BP) ΔΣ modulator which can improve the design procedure. The proposed top-down, mixed- level design platform is implemented under Cadence's Spectre environment using Verilog-A. A 2^nd order CT BP ΔΣ modulator for WCDMA applications. The central frequency of this modulator is at 100MHz and the quantizer operates at 400MHz clock frequency. The modulator is designed using TSMC 0.35μm CMOS technology with a supply voltage of 3.3V. The simulated maximum SNDR is 40dB for a 3.84MHz bandwidth, which corresponds to a resolution of 6 bits.

Original language	English
Title of host publication	Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Pages	1390-1393
Number of pages	4
DOIs	https://doi.org/10.1109/APCCAS.2008.4746289
Publication status	Published - 2008
Event	APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems - Macao, China Duration: 2008 Nov 30 → 2008 Dec 3

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Other

Other	APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Country/Territory	China
City	Macao
Period	08-11-30 → 08-12-03

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/APCCAS.2008.4746289

Cite this

Chu, H. Y., Yang, C. H., Leng, C. W., & Tsai, C. H. (2008). A Top-down, mixed-level design methodology for CT BP ΔΣ modulator using verilog-A. In Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (pp. 1390-1393). [4746289] (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). https://doi.org/10.1109/APCCAS.2008.4746289

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title = "A Top-down, mixed-level design methodology for CT BP ΔΣ modulator using verilog-A",

abstract = "This paper presents a design methodology of a continuous-time (CT) Band-pass (BP) ΔΣ modulator which can improve the design procedure. The proposed top-down, mixed- level design platform is implemented under Cadence's Spectre environment using Verilog-A. A 2nd order CT BP ΔΣ modulator for WCDMA applications. The central frequency of this modulator is at 100MHz and the quantizer operates at 400MHz clock frequency. The modulator is designed using TSMC 0.35μm CMOS technology with a supply voltage of 3.3V. The simulated maximum SNDR is 40dB for a 3.84MHz bandwidth, which corresponds to a resolution of 6 bits.",

author = "Chu, {Hung Yuan} and Yang, {Chun Hung} and Leng, {Chi Wai} and Tsai, {Chien Hung}",

year = "2008",

doi = "10.1109/APCCAS.2008.4746289",

language = "English",

isbn = "9781424423422",

series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

pages = "1390--1393",

booktitle = "Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems",

note = "APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems ; Conference date: 30-11-2008 Through 03-12-2008",

}

Chu, HY, Yang, CH, Leng, CW & Tsai, CH 2008, A Top-down, mixed-level design methodology for CT BP ΔΣ modulator using verilog-A. in Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems., 4746289, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 1390-1393, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, China, 08-11-30. https://doi.org/10.1109/APCCAS.2008.4746289

A Top-down, mixed-level design methodology for CT BP ΔΣ modulator using verilog-A. / Chu, Hung Yuan; Yang, Chun Hung; Leng, Chi Wai; Tsai, Chien Hung.

Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems. 2008. p. 1390-1393 4746289 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - This paper presents a design methodology of a continuous-time (CT) Band-pass (BP) ΔΣ modulator which can improve the design procedure. The proposed top-down, mixed- level design platform is implemented under Cadence's Spectre environment using Verilog-A. A 2nd order CT BP ΔΣ modulator for WCDMA applications. The central frequency of this modulator is at 100MHz and the quantizer operates at 400MHz clock frequency. The modulator is designed using TSMC 0.35μm CMOS technology with a supply voltage of 3.3V. The simulated maximum SNDR is 40dB for a 3.84MHz bandwidth, which corresponds to a resolution of 6 bits.

AB - This paper presents a design methodology of a continuous-time (CT) Band-pass (BP) ΔΣ modulator which can improve the design procedure. The proposed top-down, mixed- level design platform is implemented under Cadence's Spectre environment using Verilog-A. A 2nd order CT BP ΔΣ modulator for WCDMA applications. The central frequency of this modulator is at 100MHz and the quantizer operates at 400MHz clock frequency. The modulator is designed using TSMC 0.35μm CMOS technology with a supply voltage of 3.3V. The simulated maximum SNDR is 40dB for a 3.84MHz bandwidth, which corresponds to a resolution of 6 bits.

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A Top-down, mixed-level design methodology for CT BP ΔΣ modulator using verilog-A

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