The automation of combinational circuits synthesis has again gained interest since the introduction of the concept of silicon compilers. It can result in reduction of design time, significant improvements of the circuitry, and guarantee functional correctness. This paper describes VAR, a transformational approach for obtaining multilevel logic synthesis results. Suppressed variable permutation and complementation (SVPC) transformations which are powerful and can be economically realized are introduced. Each SVPC transformation can be viewed as the identify on the n-cube except on an (n-r)-subcube (defined by r fixed coordinates) where the acting is like a variable permutation and complementation (VPC) transformation on n-r variables (the free variables). VAR is based on transforming the input functions to predefined goal functions by SVPC transformations. A transformation tree is obtained and the transformations on the transformation tree are collapsed and further simplified to obtain an economical circuit, We believe that it is an interesting area that is worth more investigation.
|Number of pages||10|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|Publication status||Published - 1991 Mar|
All Science Journal Classification (ASJC) codes
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering