A unified test and debug platform for SOC design

Kuen-Jong Lee, Chin Yao Chang, Alan Su, Si Yuan Liang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

As the complexity of System-on-a-Chip (SOC) design keeps growing rapidly, efficient and economic testing and debugging for complex circuits at silicon stage has become extremely important. In this paper we present a unified platform that facilitates efficient on-chip testing and silicon debugging in a PC-based environment. Test techniques including scan and BIST, and debug functions including online tracing, hardware breakpoint insertion and cycle-based single-stepping, are supported in this platform. An automatic design tool is also developed to simplify the generation and application ofthe platform. With this platform users can easily carry out structural testing with the scan or BIST test mode, functional verification with the on-line tracing mode, and fault diagnosis with the single-step mode.

Original languageEnglish
Title of host publicationASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
Pages577-580
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha, China
Duration: 2009 Oct 202009 Oct 23

Publication series

NameASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

Other

Other2009 8th IEEE International Conference on ASIC, ASICON 2009
CountryChina
CityChangsha
Period09-10-2009-10-23

Fingerprint

Built-in self test
Testing
Silicon
Failure analysis
Hardware
Economics
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Lee, K-J., Chang, C. Y., Su, A., & Liang, S. Y. (2009). A unified test and debug platform for SOC design. In ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC (pp. 577-580). [5351351] (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC). https://doi.org/10.1109/ASICON.2009.5351351
Lee, Kuen-Jong ; Chang, Chin Yao ; Su, Alan ; Liang, Si Yuan. / A unified test and debug platform for SOC design. ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC. 2009. pp. 577-580 (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC).
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abstract = "As the complexity of System-on-a-Chip (SOC) design keeps growing rapidly, efficient and economic testing and debugging for complex circuits at silicon stage has become extremely important. In this paper we present a unified platform that facilitates efficient on-chip testing and silicon debugging in a PC-based environment. Test techniques including scan and BIST, and debug functions including online tracing, hardware breakpoint insertion and cycle-based single-stepping, are supported in this platform. An automatic design tool is also developed to simplify the generation and application ofthe platform. With this platform users can easily carry out structural testing with the scan or BIST test mode, functional verification with the on-line tracing mode, and fault diagnosis with the single-step mode.",
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Lee, K-J, Chang, CY, Su, A & Liang, SY 2009, A unified test and debug platform for SOC design. in ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC., 5351351, ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC, pp. 577-580, 2009 8th IEEE International Conference on ASIC, ASICON 2009, Changsha, China, 09-10-20. https://doi.org/10.1109/ASICON.2009.5351351

A unified test and debug platform for SOC design. / Lee, Kuen-Jong; Chang, Chin Yao; Su, Alan; Liang, Si Yuan.

ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC. 2009. p. 577-580 5351351 (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Lee K-J, Chang CY, Su A, Liang SY. A unified test and debug platform for SOC design. In ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC. 2009. p. 577-580. 5351351. (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC). https://doi.org/10.1109/ASICON.2009.5351351