A unified test and debug platform for SOC design

Kuen-Jong Lee; Chin Yao Chang; Alan Su; Si Yuan Liang

doi:10.1109/ASICON.2009.5351351

A unified test and debug platform for SOC design

Kuen-Jong Lee, Chin Yao Chang, Alan Su, Si Yuan Liang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

As the complexity of System-on-a-Chip (SOC) design keeps growing rapidly, efficient and economic testing and debugging for complex circuits at silicon stage has become extremely important. In this paper we present a unified platform that facilitates efficient on-chip testing and silicon debugging in a PC-based environment. Test techniques including scan and BIST, and debug functions including online tracing, hardware breakpoint insertion and cycle-based single-stepping, are supported in this platform. An automatic design tool is also developed to simplify the generation and application ofthe platform. With this platform users can easily carry out structural testing with the scan or BIST test mode, functional verification with the on-line tracing mode, and fault diagnosis with the single-step mode.

Original language	English
Title of host publication	ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC
Pages	577-580
Number of pages	4
DOIs	https://doi.org/10.1109/ASICON.2009.5351351
Publication status	Published - 2009 Dec 1
Event	2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha, China Duration: 2009 Oct 20 → 2009 Oct 23

Publication series

Name	ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

Other

Other	2009 8th IEEE International Conference on ASIC, ASICON 2009
Country	China
City	Changsha
Period	09-10-20 → 09-10-23

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASICON.2009.5351351

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@inproceedings{dd33710b2e70488fb562d199ce18b4c4,

title = "A unified test and debug platform for SOC design",

abstract = "As the complexity of System-on-a-Chip (SOC) design keeps growing rapidly, efficient and economic testing and debugging for complex circuits at silicon stage has become extremely important. In this paper we present a unified platform that facilitates efficient on-chip testing and silicon debugging in a PC-based environment. Test techniques including scan and BIST, and debug functions including online tracing, hardware breakpoint insertion and cycle-based single-stepping, are supported in this platform. An automatic design tool is also developed to simplify the generation and application ofthe platform. With this platform users can easily carry out structural testing with the scan or BIST test mode, functional verification with the on-line tracing mode, and fault diagnosis with the single-step mode.",

author = "Kuen-Jong Lee and Chang, {Chin Yao} and Alan Su and Liang, {Si Yuan}",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/ASICON.2009.5351351",

language = "English",

isbn = "9781424438686",

series = "ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC",

pages = "577--580",

booktitle = "ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC",

note = "2009 8th IEEE International Conference on ASIC, ASICON 2009 ; Conference date: 20-10-2009 Through 23-10-2009",

}

Lee, K-J, Chang, CY, Su, A & Liang, SY 2009, A unified test and debug platform for SOC design. in ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC., 5351351, ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC, pp. 577-580, 2009 8th IEEE International Conference on ASIC, ASICON 2009, Changsha, China, 09-10-20. https://doi.org/10.1109/ASICON.2009.5351351

A unified test and debug platform for SOC design. / Lee, Kuen-Jong; Chang, Chin Yao; Su, Alan; Liang, Si Yuan.

ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC. 2009. p. 577-580 5351351 (ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A unified test and debug platform for SOC design

AU - Lee, Kuen-Jong

AU - Chang, Chin Yao

AU - Su, Alan

AU - Liang, Si Yuan

PY - 2009/12/1

Y1 - 2009/12/1

N2 - As the complexity of System-on-a-Chip (SOC) design keeps growing rapidly, efficient and economic testing and debugging for complex circuits at silicon stage has become extremely important. In this paper we present a unified platform that facilitates efficient on-chip testing and silicon debugging in a PC-based environment. Test techniques including scan and BIST, and debug functions including online tracing, hardware breakpoint insertion and cycle-based single-stepping, are supported in this platform. An automatic design tool is also developed to simplify the generation and application ofthe platform. With this platform users can easily carry out structural testing with the scan or BIST test mode, functional verification with the on-line tracing mode, and fault diagnosis with the single-step mode.

AB - As the complexity of System-on-a-Chip (SOC) design keeps growing rapidly, efficient and economic testing and debugging for complex circuits at silicon stage has become extremely important. In this paper we present a unified platform that facilitates efficient on-chip testing and silicon debugging in a PC-based environment. Test techniques including scan and BIST, and debug functions including online tracing, hardware breakpoint insertion and cycle-based single-stepping, are supported in this platform. An automatic design tool is also developed to simplify the generation and application ofthe platform. With this platform users can easily carry out structural testing with the scan or BIST test mode, functional verification with the on-line tracing mode, and fault diagnosis with the single-step mode.

UR - http://www.scopus.com/inward/record.url?scp=77949381019&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77949381019&partnerID=8YFLogxK

U2 - 10.1109/ASICON.2009.5351351

DO - 10.1109/ASICON.2009.5351351

M3 - Conference contribution

AN - SCOPUS:77949381019

SN - 9781424438686

T3 - ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

SP - 577

EP - 580

BT - ASICON 2009 - Proceedings, 2009 8th IEEE International Conference on ASIC

T2 - 2009 8th IEEE International Conference on ASIC, ASICON 2009

Y2 - 20 October 2009 through 23 October 2009

ER -