A universal March pattern generator for testing embedded memory cores

Wei Lun Wang, Kuen-Jong Lee, Jhing Fa Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper we present a systematic procedure to integrate multiple march algorithms into a universal embedded test pattern generator to test the various kinds of memory cores in a system-on-a-chip. With a low hardware overhead, a satisfied high fault coverage can be achieved by using the proposed test pattern generator.

Original languageEnglish
Title of host publicationProceedings - 12th Annual IEEE International ASIC/SOC Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages228-232
Number of pages5
ISBN (Electronic)0780356322, 9780780356320
DOIs
Publication statusPublished - 1999 Jan 1
Event12th Annual IEEE International ASIC/SOC Conference - Washington, United States
Duration: 1999 Sep 151999 Sep 18

Publication series

NameProceedings - 12th Annual IEEE International ASIC/SOC Conference

Other

Other12th Annual IEEE International ASIC/SOC Conference
CountryUnited States
CityWashington
Period99-09-1599-09-18

Fingerprint

Hardware
Data storage equipment
Testing

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Wang, W. L., Lee, K-J., & Wang, J. F. (1999). A universal March pattern generator for testing embedded memory cores. In Proceedings - 12th Annual IEEE International ASIC/SOC Conference (pp. 228-232). [806510] (Proceedings - 12th Annual IEEE International ASIC/SOC Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.1999.806510
Wang, Wei Lun ; Lee, Kuen-Jong ; Wang, Jhing Fa. / A universal March pattern generator for testing embedded memory cores. Proceedings - 12th Annual IEEE International ASIC/SOC Conference. Institute of Electrical and Electronics Engineers Inc., 1999. pp. 228-232 (Proceedings - 12th Annual IEEE International ASIC/SOC Conference).
@inproceedings{0c953416d1c04fd49930566f347df27c,
title = "A universal March pattern generator for testing embedded memory cores",
abstract = "In this paper we present a systematic procedure to integrate multiple march algorithms into a universal embedded test pattern generator to test the various kinds of memory cores in a system-on-a-chip. With a low hardware overhead, a satisfied high fault coverage can be achieved by using the proposed test pattern generator.",
author = "Wang, {Wei Lun} and Kuen-Jong Lee and Wang, {Jhing Fa}",
year = "1999",
month = "1",
day = "1",
doi = "10.1109/ASIC.1999.806510",
language = "English",
series = "Proceedings - 12th Annual IEEE International ASIC/SOC Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "228--232",
booktitle = "Proceedings - 12th Annual IEEE International ASIC/SOC Conference",
address = "United States",

}

Wang, WL, Lee, K-J & Wang, JF 1999, A universal March pattern generator for testing embedded memory cores. in Proceedings - 12th Annual IEEE International ASIC/SOC Conference., 806510, Proceedings - 12th Annual IEEE International ASIC/SOC Conference, Institute of Electrical and Electronics Engineers Inc., pp. 228-232, 12th Annual IEEE International ASIC/SOC Conference, Washington, United States, 99-09-15. https://doi.org/10.1109/ASIC.1999.806510

A universal March pattern generator for testing embedded memory cores. / Wang, Wei Lun; Lee, Kuen-Jong; Wang, Jhing Fa.

Proceedings - 12th Annual IEEE International ASIC/SOC Conference. Institute of Electrical and Electronics Engineers Inc., 1999. p. 228-232 806510 (Proceedings - 12th Annual IEEE International ASIC/SOC Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - A universal March pattern generator for testing embedded memory cores

AU - Wang, Wei Lun

AU - Lee, Kuen-Jong

AU - Wang, Jhing Fa

PY - 1999/1/1

Y1 - 1999/1/1

N2 - In this paper we present a systematic procedure to integrate multiple march algorithms into a universal embedded test pattern generator to test the various kinds of memory cores in a system-on-a-chip. With a low hardware overhead, a satisfied high fault coverage can be achieved by using the proposed test pattern generator.

AB - In this paper we present a systematic procedure to integrate multiple march algorithms into a universal embedded test pattern generator to test the various kinds of memory cores in a system-on-a-chip. With a low hardware overhead, a satisfied high fault coverage can be achieved by using the proposed test pattern generator.

UR - http://www.scopus.com/inward/record.url?scp=28344455547&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=28344455547&partnerID=8YFLogxK

U2 - 10.1109/ASIC.1999.806510

DO - 10.1109/ASIC.1999.806510

M3 - Conference contribution

T3 - Proceedings - 12th Annual IEEE International ASIC/SOC Conference

SP - 228

EP - 232

BT - Proceedings - 12th Annual IEEE International ASIC/SOC Conference

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Wang WL, Lee K-J, Wang JF. A universal March pattern generator for testing embedded memory cores. In Proceedings - 12th Annual IEEE International ASIC/SOC Conference. Institute of Electrical and Electronics Engineers Inc. 1999. p. 228-232. 806510. (Proceedings - 12th Annual IEEE International ASIC/SOC Conference). https://doi.org/10.1109/ASIC.1999.806510