A universal March pattern generator for testing embedded memory cores

Wei Lun Wang, Kuen Jong Lee, Jhing Fa Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper we present a systematic procedure to integrate multiple march algorithms into a universal embedded test pattern generator to test the various kinds of memory cores in a system-on-a-chip. With a low hardware overhead, a satisfied high fault coverage can be achieved by using the proposed test pattern generator.

Original languageEnglish
Title of host publicationProceedings - 12th Annual IEEE International ASIC/SOC Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages228-232
Number of pages5
ISBN (Electronic)0780356322, 9780780356320
DOIs
Publication statusPublished - 1999
Event12th Annual IEEE International ASIC/SOC Conference - Washington, United States
Duration: 1999 Sept 151999 Sept 18

Publication series

NameProceedings - 12th Annual IEEE International ASIC/SOC Conference

Other

Other12th Annual IEEE International ASIC/SOC Conference
Country/TerritoryUnited States
CityWashington
Period99-09-1599-09-18

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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