Abstract
In this paper we present a systematic procedure to integrate multiple march algorithms into a universal embedded test pattern generator to test the various kinds of memory cores in a system-on-a-chip. With a low hardware overhead, a satisfied high fault coverage can be achieved by using the proposed test pattern generator.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 12th Annual IEEE International ASIC/SOC Conference |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 228-232 |
| Number of pages | 5 |
| ISBN (Electronic) | 0780356322, 9780780356320 |
| DOIs | |
| Publication status | Published - 1999 Jan 1 |
| Event | 12th Annual IEEE International ASIC/SOC Conference - Washington, United States Duration: 1999 Sep 15 → 1999 Sep 18 |
Publication series
| Name | Proceedings - 12th Annual IEEE International ASIC/SOC Conference |
|---|
Other
| Other | 12th Annual IEEE International ASIC/SOC Conference |
|---|---|
| Country | United States |
| City | Washington |
| Period | 99-09-15 → 99-09-18 |
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
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Cite this
Wang, W. L., Lee, K. J., & Wang, J. F. (1999). A universal March pattern generator for testing embedded memory cores. In Proceedings - 12th Annual IEEE International ASIC/SOC Conference (pp. 228-232). [806510] (Proceedings - 12th Annual IEEE International ASIC/SOC Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.1999.806510