Abstract
In this paper we present a systematic procedure to integrate multiple march algorithms into a universal embedded test pattern generator to test the various kinds of memory cores in a system-on-a-chip. With a low hardware overhead, a satisfied high fault coverage can be achieved by using the proposed test pattern generator.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 12th Annual IEEE International ASIC/SOC Conference |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 228-232 |
| Number of pages | 5 |
| ISBN (Electronic) | 0780356322, 9780780356320 |
| DOIs | |
| Publication status | Published - 1999 Jan 1 |
| Event | 12th Annual IEEE International ASIC/SOC Conference - Washington, United States Duration: 1999 Sep 15 → 1999 Sep 18 |
Publication series
| Name | Proceedings - 12th Annual IEEE International ASIC/SOC Conference |
|---|
Other
| Other | 12th Annual IEEE International ASIC/SOC Conference |
|---|---|
| Country | United States |
| City | Washington |
| Period | 99-09-15 → 99-09-18 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
}
A universal March pattern generator for testing embedded memory cores. / Wang, Wei Lun; Lee, Kuen-Jong; Wang, Jhing Fa.
Proceedings - 12th Annual IEEE International ASIC/SOC Conference. Institute of Electrical and Electronics Engineers Inc., 1999. p. 228-232 806510 (Proceedings - 12th Annual IEEE International ASIC/SOC Conference).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A universal March pattern generator for testing embedded memory cores
AU - Wang, Wei Lun
AU - Lee, Kuen-Jong
AU - Wang, Jhing Fa
PY - 1999/1/1
Y1 - 1999/1/1
N2 - In this paper we present a systematic procedure to integrate multiple march algorithms into a universal embedded test pattern generator to test the various kinds of memory cores in a system-on-a-chip. With a low hardware overhead, a satisfied high fault coverage can be achieved by using the proposed test pattern generator.
AB - In this paper we present a systematic procedure to integrate multiple march algorithms into a universal embedded test pattern generator to test the various kinds of memory cores in a system-on-a-chip. With a low hardware overhead, a satisfied high fault coverage can be achieved by using the proposed test pattern generator.
UR - http://www.scopus.com/inward/record.url?scp=28344455547&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=28344455547&partnerID=8YFLogxK
U2 - 10.1109/ASIC.1999.806510
DO - 10.1109/ASIC.1999.806510
M3 - Conference contribution
T3 - Proceedings - 12th Annual IEEE International ASIC/SOC Conference
SP - 228
EP - 232
BT - Proceedings - 12th Annual IEEE International ASIC/SOC Conference
PB - Institute of Electrical and Electronics Engineers Inc.
ER -