A universal March pattern generator for testing embedded memory cores

Wei Lun Wang; Kuen Jong Lee; Jhing Fa Wang

doi:10.1109/ASIC.1999.806510

A universal March pattern generator for testing embedded memory cores

Wei Lun Wang, Kuen Jong Lee, Jhing Fa Wang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

In this paper we present a systematic procedure to integrate multiple march algorithms into a universal embedded test pattern generator to test the various kinds of memory cores in a system-on-a-chip. With a low hardware overhead, a satisfied high fault coverage can be achieved by using the proposed test pattern generator.

Original language	English
Title of host publication	Proceedings - 12th Annual IEEE International ASIC/SOC Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	228-232
Number of pages	5
ISBN (Electronic)	0780356322, 9780780356320
DOIs	https://doi.org/10.1109/ASIC.1999.806510
Publication status	Published - 1999
Event	12th Annual IEEE International ASIC/SOC Conference - Washington, United States Duration: 1999 Sept 15 → 1999 Sept 18

Publication series

Name	Proceedings - 12th Annual IEEE International ASIC/SOC Conference

Other

Other	12th Annual IEEE International ASIC/SOC Conference
Country/Territory	United States
City	Washington
Period	99-09-15 → 99-09-18

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASIC.1999.806510

Cite this

Wang, W. L., Lee, K. J., & Wang, J. F. (1999). A universal March pattern generator for testing embedded memory cores. In Proceedings - 12th Annual IEEE International ASIC/SOC Conference (pp. 228-232). Article 806510 (Proceedings - 12th Annual IEEE International ASIC/SOC Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.1999.806510

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title = "A universal March pattern generator for testing embedded memory cores",

abstract = "In this paper we present a systematic procedure to integrate multiple march algorithms into a universal embedded test pattern generator to test the various kinds of memory cores in a system-on-a-chip. With a low hardware overhead, a satisfied high fault coverage can be achieved by using the proposed test pattern generator.",

author = "Wang, {Wei Lun} and Lee, {Kuen Jong} and Wang, {Jhing Fa}",

note = "Publisher Copyright: {\textcopyright} 1999 IEEE.; 12th Annual IEEE International ASIC/SOC Conference ; Conference date: 15-09-1999 Through 18-09-1999",

year = "1999",

doi = "10.1109/ASIC.1999.806510",

language = "English",

series = "Proceedings - 12th Annual IEEE International ASIC/SOC Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "228--232",

booktitle = "Proceedings - 12th Annual IEEE International ASIC/SOC Conference",

address = "United States",

}

Wang, WL, Lee, KJ & Wang, JF 1999, A universal March pattern generator for testing embedded memory cores. in Proceedings - 12th Annual IEEE International ASIC/SOC Conference., 806510, Proceedings - 12th Annual IEEE International ASIC/SOC Conference, Institute of Electrical and Electronics Engineers Inc., pp. 228-232, 12th Annual IEEE International ASIC/SOC Conference, Washington, United States, 99-09-15. https://doi.org/10.1109/ASIC.1999.806510

A universal March pattern generator for testing embedded memory cores. / Wang, Wei Lun; Lee, Kuen Jong; Wang, Jhing Fa.
Proceedings - 12th Annual IEEE International ASIC/SOC Conference. Institute of Electrical and Electronics Engineers Inc., 1999. p. 228-232 806510 (Proceedings - 12th Annual IEEE International ASIC/SOC Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Lee, Kuen Jong

AU - Wang, Jhing Fa

PY - 1999

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N2 - In this paper we present a systematic procedure to integrate multiple march algorithms into a universal embedded test pattern generator to test the various kinds of memory cores in a system-on-a-chip. With a low hardware overhead, a satisfied high fault coverage can be achieved by using the proposed test pattern generator.

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M3 - Conference contribution

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T3 - Proceedings - 12th Annual IEEE International ASIC/SOC Conference

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BT - Proceedings - 12th Annual IEEE International ASIC/SOC Conference

PB - Institute of Electrical and Electronics Engineers Inc.

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ER -

A universal March pattern generator for testing embedded memory cores

Abstract

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