A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs

Lih Yih Chiou, Chi Ray Huang, Chang Chieh Cheng, Jing Yu Huang, Wei Suo Ling

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Read stability issues resulting from PVT variations are increasingly important when operating voltage entering the near-threshold region. An adaptive local column sensing keeper scheme is proposed to detect and generate an appropriate keeper current to mitigate the issue and, simultaneously, to reduce power consumption. Based on post-layout simulations using 90nm technology, the SRAM macro with the proposed sensing scheme can support near-threshold and sub-threshold operation and achieve up to 24% power reduction when compared with the conventional design in the worst-case corner.

Original languageEnglish
Title of host publication2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728106557
DOIs
Publication statusPublished - 2019 Apr
Event2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan
Duration: 2019 Apr 222019 Apr 25

Publication series

Name2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Conference

Conference2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
CountryTaiwan
CityHsinchu
Period19-04-2219-04-25

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Instrumentation
  • Computer Networks and Communications
  • Hardware and Architecture

Fingerprint Dive into the research topics of 'A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs'. Together they form a unique fingerprint.

Cite this