A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs

Lih Yih Chiou; Chi Ray Huang; Chang Chieh Cheng; Jing Yu Huang; Wei Suo Ling

doi:10.1109/VLSI-DAT.2019.8741606

A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs

Lih Yih Chiou, Chi Ray Huang, Chang Chieh Cheng, Jing Yu Huang, Wei Suo Ling

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Read stability issues resulting from PVT variations are increasingly important when operating voltage entering the near-threshold region. An adaptive local column sensing keeper scheme is proposed to detect and generate an appropriate keeper current to mitigate the issue and, simultaneously, to reduce power consumption. Based on post-layout simulations using 90nm technology, the SRAM macro with the proposed sensing scheme can support near-threshold and sub-threshold operation and achieve up to 24% power reduction when compared with the conventional design in the worst-case corner.

Original language	English
Title of host publication	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728106557
DOIs	https://doi.org/10.1109/VLSI-DAT.2019.8741606
Publication status	Published - 2019 Apr
Event	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan Duration: 2019 Apr 22 → 2019 Apr 25

Publication series

Name	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Conference

Conference	2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
Country/Territory	Taiwan
City	Hsinchu
Period	19-04-22 → 19-04-25

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
Instrumentation
Computer Networks and Communications
Hardware and Architecture

Access to Document

10.1109/VLSI-DAT.2019.8741606

Cite this

Chiou, L. Y., Huang, C. R., Cheng, C. C., Huang, J. Y., & Ling, W. S. (2019). A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs. In 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 Article 8741606 (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2019.8741606

@inproceedings{51b146f490de442cb3d62df12a574b02,

title = "A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs",

abstract = "Read stability issues resulting from PVT variations are increasingly important when operating voltage entering the near-threshold region. An adaptive local column sensing keeper scheme is proposed to detect and generate an appropriate keeper current to mitigate the issue and, simultaneously, to reduce power consumption. Based on post-layout simulations using 90nm technology, the SRAM macro with the proposed sensing scheme can support near-threshold and sub-threshold operation and achieve up to 24% power reduction when compared with the conventional design in the worst-case corner.",

author = "Chiou, {Lih Yih} and Huang, {Chi Ray} and Cheng, {Chang Chieh} and Huang, {Jing Yu} and Ling, {Wei Suo}",

year = "2019",

month = apr,

doi = "10.1109/VLSI-DAT.2019.8741606",

language = "English",

series = "2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019",

address = "United States",

note = "2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 ; Conference date: 22-04-2019 Through 25-04-2019",

}

Chiou, LY, Huang, CR, Cheng, CC, Huang, JY & Ling, WS 2019, A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs. in 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019., 8741606, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Institute of Electrical and Electronics Engineers Inc., 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, 19-04-22. https://doi.org/10.1109/VLSI-DAT.2019.8741606

A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs. / Chiou, Lih Yih; Huang, Chi Ray; Cheng, Chang Chieh et al.
2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8741606 (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs

AU - Chiou, Lih Yih

AU - Huang, Chi Ray

AU - Cheng, Chang Chieh

AU - Huang, Jing Yu

AU - Ling, Wei Suo

PY - 2019/4

Y1 - 2019/4

N2 - Read stability issues resulting from PVT variations are increasingly important when operating voltage entering the near-threshold region. An adaptive local column sensing keeper scheme is proposed to detect and generate an appropriate keeper current to mitigate the issue and, simultaneously, to reduce power consumption. Based on post-layout simulations using 90nm technology, the SRAM macro with the proposed sensing scheme can support near-threshold and sub-threshold operation and achieve up to 24% power reduction when compared with the conventional design in the worst-case corner.

AB - Read stability issues resulting from PVT variations are increasingly important when operating voltage entering the near-threshold region. An adaptive local column sensing keeper scheme is proposed to detect and generate an appropriate keeper current to mitigate the issue and, simultaneously, to reduce power consumption. Based on post-layout simulations using 90nm technology, the SRAM macro with the proposed sensing scheme can support near-threshold and sub-threshold operation and achieve up to 24% power reduction when compared with the conventional design in the worst-case corner.

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DO - 10.1109/VLSI-DAT.2019.8741606

M3 - Conference contribution

T3 - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

BT - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Y2 - 22 April 2019 through 25 April 2019

ER -

Chiou LY, Huang CR, Cheng CC, Huang JY, Ling WS. A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs. In 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8741606. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019). doi: 10.1109/VLSI-DAT.2019.8741606

A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs

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