A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs

Lih-Yih Chiou, Chi Ray Huang, Chang Chieh Cheng, Jing Yu Huang, Wei Suo Ling

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Read stability issues resulting from PVT variations are increasingly important when operating voltage entering the near-threshold region. An adaptive local column sensing keeper scheme is proposed to detect and generate an appropriate keeper current to mitigate the issue and, simultaneously, to reduce power consumption. Based on post-layout simulations using 90nm technology, the SRAM macro with the proposed sensing scheme can support near-threshold and sub-threshold operation and achieve up to 24% power reduction when compared with the conventional design in the worst-case corner.

Original languageEnglish
Title of host publication2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728106557
DOIs
Publication statusPublished - 2019 Apr 1
Event2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan
Duration: 2019 Apr 222019 Apr 25

Publication series

Name2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Conference

Conference2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
CountryTaiwan
CityHsinchu
Period19-04-2219-04-25

Fingerprint

Static random access storage
Macros
Electric power utilization
leakage
thresholds
Electric potential
layouts
electric potential
simulation

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Instrumentation
  • Computer Networks and Communications
  • Hardware and Architecture

Cite this

Chiou, L-Y., Huang, C. R., Cheng, C. C., Huang, J. Y., & Ling, W. S. (2019). A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs. In 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 [8741606] (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2019.8741606
Chiou, Lih-Yih ; Huang, Chi Ray ; Cheng, Chang Chieh ; Huang, Jing Yu ; Ling, Wei Suo. / A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs. 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).
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title = "A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs",
abstract = "Read stability issues resulting from PVT variations are increasingly important when operating voltage entering the near-threshold region. An adaptive local column sensing keeper scheme is proposed to detect and generate an appropriate keeper current to mitigate the issue and, simultaneously, to reduce power consumption. Based on post-layout simulations using 90nm technology, the SRAM macro with the proposed sensing scheme can support near-threshold and sub-threshold operation and achieve up to 24{\%} power reduction when compared with the conventional design in the worst-case corner.",
author = "Lih-Yih Chiou and Huang, {Chi Ray} and Cheng, {Chang Chieh} and Huang, {Jing Yu} and Ling, {Wei Suo}",
year = "2019",
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language = "English",
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booktitle = "2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019",
address = "United States",

}

Chiou, L-Y, Huang, CR, Cheng, CC, Huang, JY & Ling, WS 2019, A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs. in 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019., 8741606, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Institute of Electrical and Electronics Engineers Inc., 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, 19-04-22. https://doi.org/10.1109/VLSI-DAT.2019.8741606

A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs. / Chiou, Lih-Yih; Huang, Chi Ray; Cheng, Chang Chieh; Huang, Jing Yu; Ling, Wei Suo.

2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8741606 (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Chiou L-Y, Huang CR, Cheng CC, Huang JY, Ling WS. A variation-tolerant bitline leakage sensing scheme for near-threshold SRAMs. In 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8741606. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019). https://doi.org/10.1109/VLSI-DAT.2019.8741606