Accurate delay model and experimental verification for current/voltage mode on-chip interconnects

Rizwan Bashirullah; Wentai Liu; Ralph Cavin

Accurate delay model and experimental verification for current/voltage mode on-chip interconnects

Rizwan Bashirullah, Wentai Liu, Ralph Cavin

Department of Biomedical Engineering

Research output: Contribution to journal › Conference article › peer-review

Abstract

A simple yet accurate closed-form delay expression for inverter driven on-chip interconnects with arbitrary receive-end termination is presented. The solution can be used for both resistive and capacitive termination to adequately model current and voltage mode sensing schemes. The model is extended to consider fast input slope and input-to-output capacitance effects of a CMOS inverter. A test chip fabricated in AMI 1.6μm is used to experimentally verify the proposed model. Further analysis shows that the model can be used for sub-micrometer process to accurately estimate delay and bandwidth performance of long on-chip interconnects.

Original language	English
Pages (from-to)	V169-V172
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	5
Publication status	Published - 2003
Event	Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand Duration: 2003 May 25 → 2003 May 28

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

@article{96d3504682ed420183c4fa8f207b16cc,

title = "Accurate delay model and experimental verification for current/voltage mode on-chip interconnects",

abstract = "A simple yet accurate closed-form delay expression for inverter driven on-chip interconnects with arbitrary receive-end termination is presented. The solution can be used for both resistive and capacitive termination to adequately model current and voltage mode sensing schemes. The model is extended to consider fast input slope and input-to-output capacitance effects of a CMOS inverter. A test chip fabricated in AMI 1.6μm is used to experimentally verify the proposed model. Further analysis shows that the model can be used for sub-micrometer process to accurately estimate delay and bandwidth performance of long on-chip interconnects.",

author = "Rizwan Bashirullah and Wentai Liu and Ralph Cavin",

year = "2003",

language = "English",

volume = "5",

pages = "V169--V172",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 2003 IEEE International Symposium on Circuits and Systems ; Conference date: 25-05-2003 Through 28-05-2003",

}

TY - JOUR

T1 - Accurate delay model and experimental verification for current/voltage mode on-chip interconnects

AU - Bashirullah, Rizwan

AU - Liu, Wentai

AU - Cavin, Ralph

PY - 2003

Y1 - 2003

N2 - A simple yet accurate closed-form delay expression for inverter driven on-chip interconnects with arbitrary receive-end termination is presented. The solution can be used for both resistive and capacitive termination to adequately model current and voltage mode sensing schemes. The model is extended to consider fast input slope and input-to-output capacitance effects of a CMOS inverter. A test chip fabricated in AMI 1.6μm is used to experimentally verify the proposed model. Further analysis shows that the model can be used for sub-micrometer process to accurately estimate delay and bandwidth performance of long on-chip interconnects.

AB - A simple yet accurate closed-form delay expression for inverter driven on-chip interconnects with arbitrary receive-end termination is presented. The solution can be used for both resistive and capacitive termination to adequately model current and voltage mode sensing schemes. The model is extended to consider fast input slope and input-to-output capacitance effects of a CMOS inverter. A test chip fabricated in AMI 1.6μm is used to experimentally verify the proposed model. Further analysis shows that the model can be used for sub-micrometer process to accurately estimate delay and bandwidth performance of long on-chip interconnects.

UR - http://www.scopus.com/inward/record.url?scp=0038758751&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0038758751&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0038758751

SN - 0271-4310

VL - 5

SP - V169-V172

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 2003 IEEE International Symposium on Circuits and Systems

Y2 - 25 May 2003 through 28 May 2003

ER -

Accurate delay model and experimental verification for current/voltage mode on-chip interconnects

Abstract

All Science Journal Classification (ASJC) codes

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