@inproceedings{dfb17f0f204c4fd49ad59ca2d05f9064,
title = "Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations",
abstract = "Test cost has become a critical issue for large industrial integrated circuits. Various test compression techniques have been adopted in the industry to reduce test cost. However, appropriate input and output channel counts must be selected to utilize the test compression technology best. This paper presents an efficient and effective method to estimate the test pattern counts under different compression configurations for the Embedded Deterministic Test (EDT) compression technique. In searching for the accurate estimation method, we build mathematical models that reveal the internal relationship among different compression configurations. The models are established based on novel theoretical analysis as well as actual experimental data. Accurate estimation of test pattern counts for a wide range of compression configurations can be obtained based on the results of only two ATPG runs. Experimental results on nine industrial circuits show that the average error rate of pattern count estimation is about 5%, with very few outliers. With the proposed method, a test compression designer can easily pick the best input and output channel configuration to fit the design needs.",
author = "Zheng, {Shi Xuan} and Yeh, {Chung Yu} and Lee, {Kuen Jong} and Chen Wang and Cheng, {Wu Tung} and Mark Kassab and Janusz Rajski and Reddy, {Sudhakar M.}",
note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 40th IEEE VLSI Test Symposium, VTS 2022 ; Conference date: 25-04-2022 Through 27-04-2022",
year = "2022",
doi = "10.1109/VTS52500.2021.9794207",
language = "English",
series = "Proceedings of the IEEE VLSI Test Symposium",
publisher = "IEEE Computer Society",
booktitle = "Proceedings - 2022 IEEE 40th VLSI Test Symposium, VTS 2022",
address = "United States",
}