ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs

Jinn Shyan Wang; Yung Chen Chien; Jia Hong Lin; Chun Yuan Cheng; Ying Ting Ma; Chung Hsun Huang

doi:10.1109/ASICON.2011.6157119

ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs

Jinn Shyan Wang
, Yung Chen Chien
, Jia Hong Lin
, Chun Yuan Cheng
, Ying Ting Ma
, Chung Hsun Huang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This work proposes an ADDLL/VDD-biasing co-design methodology for variation-tolerant designs. A modified ADDLL behaves as a variability sensor in the beginning of operation, and the sensing result is used by a VDD-biasing circuit to adjust the VDD of a loaded design for performance calibration. During normal operation, the ADDLL is reused as a de-skewing element for the calibrated design. With this methodology, not only the performance of the loaded design but also that of the ADDLL can be effectively adjusted toward their design specifications even under serious process variations.

Original language	English
Title of host publication	Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011
Pages	47-50
Number of pages	4
DOIs	https://doi.org/10.1109/ASICON.2011.6157119
Publication status	Published - 2011
Event	2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen, China Duration: 2011 Oct 25 → 2011 Oct 28

Publication series

Name	Proceedings of International Conference on ASIC
ISSN (Print)	2162-7541
ISSN (Electronic)	2162-755X

Other

Other	2011 IEEE 9th International Conference on ASIC, ASICON 2011
Country/Territory	China
City	Xiamen
Period	11-10-25 → 11-10-28

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASICON.2011.6157119

Cite this

Wang, J. S., Chien, Y. C., Lin, J. H., Cheng, C. Y., Ma, Y. T., & Huang, C. H. (2011). ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs. In Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011 (pp. 47-50). Article 6157119 (Proceedings of International Conference on ASIC). https://doi.org/10.1109/ASICON.2011.6157119

@inproceedings{aebb9d9c0d074356b77a2231bd0525d0,

title = "ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs",

abstract = "This work proposes an ADDLL/VDD-biasing co-design methodology for variation-tolerant designs. A modified ADDLL behaves as a variability sensor in the beginning of operation, and the sensing result is used by a VDD-biasing circuit to adjust the VDD of a loaded design for performance calibration. During normal operation, the ADDLL is reused as a de-skewing element for the calibrated design. With this methodology, not only the performance of the loaded design but also that of the ADDLL can be effectively adjusted toward their design specifications even under serious process variations.",

author = "Wang, \{Jinn Shyan\} and Chien, \{Yung Chen\} and Lin, \{Jia Hong\} and Cheng, \{Chun Yuan\} and Ma, \{Ying Ting\} and Huang, \{Chung Hsun\}",

year = "2011",

doi = "10.1109/ASICON.2011.6157119",

language = "English",

isbn = "9781612841908",

series = "Proceedings of International Conference on ASIC",

pages = "47--50",

booktitle = "Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011",

note = "2011 IEEE 9th International Conference on ASIC, ASICON 2011 ; Conference date: 25-10-2011 Through 28-10-2011",

}

Wang, JS, Chien, YC, Lin, JH, Cheng, CY, Ma, YT & Huang, CH 2011, ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs. in Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011., 6157119, Proceedings of International Conference on ASIC, pp. 47-50, 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, 11-10-25. https://doi.org/10.1109/ASICON.2011.6157119

ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs. / Wang, Jinn Shyan; Chien, Yung Chen; Lin, Jia Hong et al.
Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011. 2011. p. 47-50 6157119 (Proceedings of International Conference on ASIC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AB - This work proposes an ADDLL/VDD-biasing co-design methodology for variation-tolerant designs. A modified ADDLL behaves as a variability sensor in the beginning of operation, and the sensing result is used by a VDD-biasing circuit to adjust the VDD of a loaded design for performance calibration. During normal operation, the ADDLL is reused as a de-skewing element for the calibrated design. With this methodology, not only the performance of the loaded design but also that of the ADDLL can be effectively adjusted toward their design specifications even under serious process variations.

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Wang JS, Chien YC, Lin JH, Cheng CY, Ma YT, Huang CH. ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs. In Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011. 2011. p. 47-50. 6157119. (Proceedings of International Conference on ASIC). doi: 10.1109/ASICON.2011.6157119

ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs

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