Address compression for scalable load/store queue implementation

Yi Ying Tsai; Chia Jung Hsu; Chung Ho Chen

doi:10.1109/ISCAS.2008.4541759

Address compression for scalable load/store queue implementation

Yi Ying Tsai
, Chia Jung Hsu
, Chung Ho Chen

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Contemporary superscalar processors employ the load/store queue for memory disambiguation. A load/store queue is typically implemented with a CAM structure to search the address for collision and consequently poses scalability challenges of energy consumption and area cost. This paper proposes an address compression technique for load/store queue to improve the power efficiency and scalability. Using the proposed approach, the LSQ can reduce the energy consumption ranging from 38% to 72% and area cost ranging from 32% to 66%, depending on the compression parameter and system configuration. The approach can provide 3.08% overall processor energy reduction and causes only 0.22% performance loss at a balanced configuration.

Original language	English
Title of host publication	2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Pages	1680-1683
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2008.4541759
Publication status	Published - 2008
Event	2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States Duration: 2008 May 18 → 2008 May 21

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Country/Territory	United States
City	Seattle, WA
Period	08-05-18 → 08-05-21

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2008.4541759

Cite this

@inproceedings{2b22f80668db476ab675c88e7a835db0,

title = "Address compression for scalable load/store queue implementation",

abstract = "Contemporary superscalar processors employ the load/store queue for memory disambiguation. A load/store queue is typically implemented with a CAM structure to search the address for collision and consequently poses scalability challenges of energy consumption and area cost. This paper proposes an address compression technique for load/store queue to improve the power efficiency and scalability. Using the proposed approach, the LSQ can reduce the energy consumption ranging from 38\% to 72\% and area cost ranging from 32\% to 66\%, depending on the compression parameter and system configuration. The approach can provide 3.08\% overall processor energy reduction and causes only 0.22\% performance loss at a balanced configuration.",

author = "Tsai, \{Yi Ying\} and Hsu, \{Chia Jung\} and Chen, \{Chung Ho\}",

year = "2008",

doi = "10.1109/ISCAS.2008.4541759",

language = "English",

isbn = "9781424416844",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "1680--1683",

booktitle = "2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008",

note = "2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 ; Conference date: 18-05-2008 Through 21-05-2008",

}

Tsai, YY, Hsu, CJ & Chen, CH 2008, Address compression for scalable load/store queue implementation. in 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008., 4541759, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 1680-1683, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008, Seattle, WA, United States, 08-05-18. https://doi.org/10.1109/ISCAS.2008.4541759

Address compression for scalable load/store queue implementation. / Tsai, Yi Ying; Hsu, Chia Jung; Chen, Chung Ho.
2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008. 2008. p. 1680-1683 4541759 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Address compression for scalable load/store queue implementation

AU - Tsai, Yi Ying

AU - Hsu, Chia Jung

AU - Chen, Chung Ho

PY - 2008

Y1 - 2008

N2 - Contemporary superscalar processors employ the load/store queue for memory disambiguation. A load/store queue is typically implemented with a CAM structure to search the address for collision and consequently poses scalability challenges of energy consumption and area cost. This paper proposes an address compression technique for load/store queue to improve the power efficiency and scalability. Using the proposed approach, the LSQ can reduce the energy consumption ranging from 38% to 72% and area cost ranging from 32% to 66%, depending on the compression parameter and system configuration. The approach can provide 3.08% overall processor energy reduction and causes only 0.22% performance loss at a balanced configuration.

AB - Contemporary superscalar processors employ the load/store queue for memory disambiguation. A load/store queue is typically implemented with a CAM structure to search the address for collision and consequently poses scalability challenges of energy consumption and area cost. This paper proposes an address compression technique for load/store queue to improve the power efficiency and scalability. Using the proposed approach, the LSQ can reduce the energy consumption ranging from 38% to 72% and area cost ranging from 32% to 66%, depending on the compression parameter and system configuration. The approach can provide 3.08% overall processor energy reduction and causes only 0.22% performance loss at a balanced configuration.

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U2 - 10.1109/ISCAS.2008.4541759

DO - 10.1109/ISCAS.2008.4541759

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T3 - Proceedings - IEEE International Symposium on Circuits and Systems

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BT - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008

T2 - 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008

Y2 - 18 May 2008 through 21 May 2008

ER -

Address compression for scalable load/store queue implementation

Abstract

Publication series

Other

UN SDGs

All Science Journal Classification (ASJC) codes

Access to Document

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Cite this