TY - JOUR
T1 - Admittance-to-Digital-Impedance Converter for Wide-Frequency-Range Impedance Measurement System
AU - Lin, Hao Wei
AU - Su, Chia Ning
AU - Chen, Tse An
AU - Chen, Yi Chen
AU - Syu, Mei Jywan
AU - Wei, Chia Ling
N1 - Funding Information:
Manuscript received December 28, 2020; revised March 28, 2021; accepted April 1, 2021. Date of publication April 16, 2021; date of current version May 10, 2021. This work was supported by the Ministry of Science and Technology, Taiwan, under Grant MOST 108-2221-E-006-195-MY3 and Grant MOST 109-2221-E-006-179-MY3. The chip fabrication was supported by the Taiwan Semiconductor Research Institute (TSRI), Taiwan. The Associate Editor coordinating the review process was Dr. Tarikul Islam. (Corresponding author: Chia-Ling Wei.) Hao-Wei Lin, Tse-An Chen, Yi-Chen Chen, and Chia-Ling Wei are with the Department of Electrical Engineering, National Cheng Kung University, Tainan 701401, Taiwan (e-mail: [email protected]).
Publisher Copyright:
© 1963-2012 IEEE.
PY - 2021
Y1 - 2021
N2 - An admittance-to-digital-impedance converter (ADIC) for impedance measurement is proposed. The ADIC was integrated in a chip with a programmable sinusoidal frequency synthesizer, allowing an operating range from 0.1 Hz to 10 kHz. The frequency synthesizer generates sinusoidal voltage signals to a sample under test (SUT), and the resulting current signal from the SUT is sensed and sent to the ADIC for postprocessing. In fact, this sensed signal is proportional to the SUT admittance, rather than to its impedance. Hence, the proposed ADIC has two functions: taking the reciprocal of the sensed signal to make it proportional to impedance and converting it into a digital signal. Furthermore, two novel circuits are also proposed: a low-leakage magnitude detector that makes it possible to measure at sub-1-Hz frequencies and a stepped-pulse divider that performs an accurate dividing function. The chip was fabricated by using a 0.35- mu text{m} 2P4M mixed-signal process. According to the measured results, the maximum errors in the magnitude and phase measurements were 1.6% and 1.8°, respectively, and the proposed system was verified by measuring the concentrations of albumin solutions.
AB - An admittance-to-digital-impedance converter (ADIC) for impedance measurement is proposed. The ADIC was integrated in a chip with a programmable sinusoidal frequency synthesizer, allowing an operating range from 0.1 Hz to 10 kHz. The frequency synthesizer generates sinusoidal voltage signals to a sample under test (SUT), and the resulting current signal from the SUT is sensed and sent to the ADIC for postprocessing. In fact, this sensed signal is proportional to the SUT admittance, rather than to its impedance. Hence, the proposed ADIC has two functions: taking the reciprocal of the sensed signal to make it proportional to impedance and converting it into a digital signal. Furthermore, two novel circuits are also proposed: a low-leakage magnitude detector that makes it possible to measure at sub-1-Hz frequencies and a stepped-pulse divider that performs an accurate dividing function. The chip was fabricated by using a 0.35- mu text{m} 2P4M mixed-signal process. According to the measured results, the maximum errors in the magnitude and phase measurements were 1.6% and 1.8°, respectively, and the proposed system was verified by measuring the concentrations of albumin solutions.
UR - http://www.scopus.com/inward/record.url?scp=85104635923&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85104635923&partnerID=8YFLogxK
U2 - 10.1109/TIM.2021.3073710
DO - 10.1109/TIM.2021.3073710
M3 - Article
AN - SCOPUS:85104635923
SN - 0018-9456
VL - 70
JO - IEEE Transactions on Instrumentation and Measurement
JF - IEEE Transactions on Instrumentation and Measurement
M1 - 9406039
ER -