Advances in selective etching for nano scale salicide fabrication

Ming Mao Chu; Jung Hua Chou

doi:10.1109/NMDC.2009.5167528

Advances in selective etching for nano scale salicide fabrication

Ming Mao Chu, Jung Hua Chou

Department of Engineering Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

High temperature SPM based wet selective processing for multi-step NiPt silicide process on nanoscale CMOS structure with dual gate dense layout has been studied. The high temperature SPM process is found to have better etching selectivity between NiPt/TiN and nickel rich silicide (Ni2Si/Ni3Si2) and results in better sheet resistance (Rs) and uniformity compare to HCL based process. The high temperature SPM process window is effective for Pt and induces very low material loss. Thus, it is a better selective etching process for multi-step silicide process that can scale with the CMOS technology toward 22nm node.

Original language	English
Title of host publication	2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009
Pages	162-165
Number of pages	4
DOIs	https://doi.org/10.1109/NMDC.2009.5167528
Publication status	Published - 2009
Event	2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009 - Traverse City, MI, United States Duration: 2009 Jun 2 → 2009 Jun 5

Publication series

Name	2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009

Other

Other	2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009
Country/Territory	United States
City	Traverse City, MI
Period	09-06-02 → 09-06-05

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/NMDC.2009.5167528

Cite this

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title = "Advances in selective etching for nano scale salicide fabrication",

abstract = "High temperature SPM based wet selective processing for multi-step NiPt silicide process on nanoscale CMOS structure with dual gate dense layout has been studied. The high temperature SPM process is found to have better etching selectivity between NiPt/TiN and nickel rich silicide (Ni2Si/Ni3Si2) and results in better sheet resistance (Rs) and uniformity compare to HCL based process. The high temperature SPM process window is effective for Pt and induces very low material loss. Thus, it is a better selective etching process for multi-step silicide process that can scale with the CMOS technology toward 22nm node.",

author = "Chu, {Ming Mao} and Chou, {Jung Hua}",

year = "2009",

doi = "10.1109/NMDC.2009.5167528",

language = "English",

isbn = "9781424446964",

series = "2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009",

pages = "162--165",

booktitle = "2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009",

note = "2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009 ; Conference date: 02-06-2009 Through 05-06-2009",

}

Chu, MM & Chou, JH 2009, Advances in selective etching for nano scale salicide fabrication. in 2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009., 5167528, 2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009, pp. 162-165, 2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009, Traverse City, MI, United States, 09-06-02. https://doi.org/10.1109/NMDC.2009.5167528

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AU - Chu, Ming Mao

AU - Chou, Jung Hua

PY - 2009

Y1 - 2009

N2 - High temperature SPM based wet selective processing for multi-step NiPt silicide process on nanoscale CMOS structure with dual gate dense layout has been studied. The high temperature SPM process is found to have better etching selectivity between NiPt/TiN and nickel rich silicide (Ni2Si/Ni3Si2) and results in better sheet resistance (Rs) and uniformity compare to HCL based process. The high temperature SPM process window is effective for Pt and induces very low material loss. Thus, it is a better selective etching process for multi-step silicide process that can scale with the CMOS technology toward 22nm node.

AB - High temperature SPM based wet selective processing for multi-step NiPt silicide process on nanoscale CMOS structure with dual gate dense layout has been studied. The high temperature SPM process is found to have better etching selectivity between NiPt/TiN and nickel rich silicide (Ni2Si/Ni3Si2) and results in better sheet resistance (Rs) and uniformity compare to HCL based process. The high temperature SPM process window is effective for Pt and induces very low material loss. Thus, it is a better selective etching process for multi-step silicide process that can scale with the CMOS technology toward 22nm node.

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U2 - 10.1109/NMDC.2009.5167528

DO - 10.1109/NMDC.2009.5167528

M3 - Conference contribution

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SN - 9781424446964

T3 - 2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009

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EP - 165

BT - 2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009

T2 - 2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009

Y2 - 2 June 2009 through 5 June 2009

ER -

Advances in selective etching for nano scale salicide fabrication

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