Advances in selective etching for nano scale salicide fabrication

Ming Mao Chu, Jung Hua Chou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

High temperature SPM based wet selective processing for multi-step NiPt silicide process on nanoscale CMOS structure with dual gate dense layout has been studied. The high temperature SPM process is found to have better etching selectivity between NiPt/TiN and nickel rich silicide (Ni2Si/Ni3Si2) and results in better sheet resistance (Rs) and uniformity compare to HCL based process. The high temperature SPM process window is effective for Pt and induces very low material loss. Thus, it is a better selective etching process for multi-step silicide process that can scale with the CMOS technology toward 22nm node.

Original languageEnglish
Title of host publication2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009
Pages162-165
Number of pages4
DOIs
Publication statusPublished - 2009 Nov 23
Event2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009 - Traverse City, MI, United States
Duration: 2009 Jun 22009 Jun 5

Publication series

Name2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009

Other

Other2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009
CountryUnited States
CityTraverse City, MI
Period09-06-0209-06-05

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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