AF-test: Adaptive-frequency scan test methodology for small-delay defects

Tsung Yeh Li, Shi Yu Huang, Hsuan Jung Hsu, Chao Wen Tzeng, Chih Tsun Huang, Jing Jia Liou, Hsi Pin Ma, Po Chiun Huang, Jenn Chyou Bor, Cheng Wen Wu, Ching Cheng Tien, Mike Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Small delay defects, when escaping from traditional delay testing, could cause a device to malfunction in the field. To address this issue, we propose an adaptive-frequency test method, abbreviated as AF-test. In this method, versatile test clocks can be generated on the chip by embedding an All-Digital Phase-Locked Loop (ADPLL) into the circuit under test (CUT). Instead of measuring the exact propagation delay associated with each test pattern like previous time-consuming failing frequency signature based analysis [14], we test only up to three different test clock frequencies for each test pattern to provide the benefit of fast characterization, and thereby making it suitable for volume production test. We have successfully demonstrated the AF-test on an in-house wireless test platform called HOY system using fabricated chips. This method can not only detect small delay defects effectively but also provide a grading scheme for those marginal chips that might have the reliability problem.

Original languageEnglish
Title of host publicationProceedings - 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010
Pages340-348
Number of pages9
DOIs
Publication statusPublished - 2010 Dec 1
Event2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010 - Kyoto, Japan
Duration: 2010 Oct 62010 Oct 8

Publication series

NameProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)1550-5774

Conference

Conference2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010
CountryJapan
CityKyoto
Period10-10-0610-10-08

Fingerprint

Clocks
Defects
Phase locked loops
Networks (circuits)
Testing

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Li, T. Y., Huang, S. Y., Hsu, H. J., Tzeng, C. W., Huang, C. T., Liou, J. J., ... Wang, M. (2010). AF-test: Adaptive-frequency scan test methodology for small-delay defects. In Proceedings - 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010 (pp. 340-348). [5634926] (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). https://doi.org/10.1109/DFT.2010.48
Li, Tsung Yeh ; Huang, Shi Yu ; Hsu, Hsuan Jung ; Tzeng, Chao Wen ; Huang, Chih Tsun ; Liou, Jing Jia ; Ma, Hsi Pin ; Huang, Po Chiun ; Bor, Jenn Chyou ; Wu, Cheng Wen ; Tien, Ching Cheng ; Wang, Mike. / AF-test : Adaptive-frequency scan test methodology for small-delay defects. Proceedings - 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010. 2010. pp. 340-348 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).
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abstract = "Small delay defects, when escaping from traditional delay testing, could cause a device to malfunction in the field. To address this issue, we propose an adaptive-frequency test method, abbreviated as AF-test. In this method, versatile test clocks can be generated on the chip by embedding an All-Digital Phase-Locked Loop (ADPLL) into the circuit under test (CUT). Instead of measuring the exact propagation delay associated with each test pattern like previous time-consuming failing frequency signature based analysis [14], we test only up to three different test clock frequencies for each test pattern to provide the benefit of fast characterization, and thereby making it suitable for volume production test. We have successfully demonstrated the AF-test on an in-house wireless test platform called HOY system using fabricated chips. This method can not only detect small delay defects effectively but also provide a grading scheme for those marginal chips that might have the reliability problem.",
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Li, TY, Huang, SY, Hsu, HJ, Tzeng, CW, Huang, CT, Liou, JJ, Ma, HP, Huang, PC, Bor, JC, Wu, CW, Tien, CC & Wang, M 2010, AF-test: Adaptive-frequency scan test methodology for small-delay defects. in Proceedings - 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010., 5634926, Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 340-348, 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, 10-10-06. https://doi.org/10.1109/DFT.2010.48

AF-test : Adaptive-frequency scan test methodology for small-delay defects. / Li, Tsung Yeh; Huang, Shi Yu; Hsu, Hsuan Jung; Tzeng, Chao Wen; Huang, Chih Tsun; Liou, Jing Jia; Ma, Hsi Pin; Huang, Po Chiun; Bor, Jenn Chyou; Wu, Cheng Wen; Tien, Ching Cheng; Wang, Mike.

Proceedings - 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010. 2010. p. 340-348 5634926 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AU - Ma, Hsi Pin

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AU - Wu, Cheng Wen

AU - Tien, Ching Cheng

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Li TY, Huang SY, Hsu HJ, Tzeng CW, Huang CT, Liou JJ et al. AF-test: Adaptive-frequency scan test methodology for small-delay defects. In Proceedings - 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010. 2010. p. 340-348. 5634926. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). https://doi.org/10.1109/DFT.2010.48