Aging-aware reliable multiplier design

Yu Hung Cho, Ing Chao Lin, Yi Ming Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)


In this work, we propose an aging-aware multiplier design with a novel adaptive hold logic circuit. The multiplier is able to provide higher throughput through the variable latency and adjust itself to mitigate the performance degradation due to the aging effect. The experimental result shows our proposed multiplier has up to 62.88% performance improvement compared with the fixed-latency column-bypassing multiplier and up to 16.11% performance improvement compared with the variable-latency column-bypassing multiplier without the adaptive logic.

Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2012
Number of pages6
Publication statusPublished - 2012 Dec 1
Event25th IEEE International System-on-Chip Conference, SOCC 2012 - Niagara Falls, NY, United States
Duration: 2012 Sep 122012 Sep 14

Publication series

NameInternational System on Chip Conference
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706


Other25th IEEE International System-on-Chip Conference, SOCC 2012
CountryUnited States
CityNiagara Falls, NY

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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