TY - GEN
T1 - Aging-aware reliable multiplier design
AU - Cho, Yu Hung
AU - Lin, Ing Chao
AU - Yang, Yi Ming
PY - 2012/12/1
Y1 - 2012/12/1
N2 - In this work, we propose an aging-aware multiplier design with a novel adaptive hold logic circuit. The multiplier is able to provide higher throughput through the variable latency and adjust itself to mitigate the performance degradation due to the aging effect. The experimental result shows our proposed multiplier has up to 62.88% performance improvement compared with the fixed-latency column-bypassing multiplier and up to 16.11% performance improvement compared with the variable-latency column-bypassing multiplier without the adaptive logic.
AB - In this work, we propose an aging-aware multiplier design with a novel adaptive hold logic circuit. The multiplier is able to provide higher throughput through the variable latency and adjust itself to mitigate the performance degradation due to the aging effect. The experimental result shows our proposed multiplier has up to 62.88% performance improvement compared with the fixed-latency column-bypassing multiplier and up to 16.11% performance improvement compared with the variable-latency column-bypassing multiplier without the adaptive logic.
UR - http://www.scopus.com/inward/record.url?scp=84872510791&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84872510791&partnerID=8YFLogxK
U2 - 10.1109/SOCC.2012.6398335
DO - 10.1109/SOCC.2012.6398335
M3 - Conference contribution
AN - SCOPUS:84872510791
SN - 9781467312950
T3 - International System on Chip Conference
SP - 322
EP - 327
BT - Proceedings - IEEE International SOC Conference, SOCC 2012
T2 - 25th IEEE International System-on-Chip Conference, SOCC 2012
Y2 - 12 September 2012 through 14 September 2012
ER -