Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs = -Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column- or row-bypassing multiplier. The experimental results show that our proposed architecture with 16 x 16 and 32 x 32 column-bypassing multipliers can attain up to 62.88% and 76.28% performance improvement, respectively, compared with 16 x 16 and 32 x 32 fixed-latency column-bypassing multipliers. Furthermore, our proposed architecture with 16 x 16 and 32 x 32 row-bypassing multipliers can achieve up to 80.17% and 69.40% performance improvement as compared with 16 x 16 and 32 x 32 fixed-latency row-bypassing multipliers.
|Number of pages||13|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|Publication status||Published - 2015 Mar 1|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering