All digital phase-locked loop using active inductor oscillator and novel locking algorithm

Tzuen-Hsi Huang, Hong Yi Huang, Jen Chieh Liu, Kuo Hsing Cheng, Ching Hsing Luo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A fast locking all-digital phase-locked loop (ADPLL) with the active inductor oscillator is proposed. An LC-tank DCO with a tunable active inductor can obtain a wider operational frequency range, smaller area and higher signal quality. The proposed frequency and phase locking algorithm can achieve good jitter performance, high frequency accuracy, and low circuit complexity. The ADPLL is designed using a 0.18 um CMOS process. The operational frequency range of the ADPLL is from 318 MHz to 458 MHz. The RMS and the peak-to-peak jitters at 402 MHz are 4.2 ps and 94 ps, respectively. The core size is 390×390 um2. The power consumption is 5.4 mW at 416 MHz.

Original languageEnglish
Title of host publication2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Pages486-489
Number of pages4
DOIs
Publication statusPublished - 2011
Event2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro, Brazil
Duration: 2011 May 152011 May 18

Other

Other2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
CountryBrazil
CityRio de Janeiro
Period11-05-1511-05-18

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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