Alternative processing order with efficient architecture for adaptive deblocking filter in H.264/AVC

Chung Ming Chen, Chung-Ho Chen, Jian Ping Zeng, Yu Pin Chang, Jing Jou Tang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we study and analyze the memory reference of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. In order to reduce the number of memory references and thus improve overall system performance in an embedded system, we propose an advanced filtering process order with an efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the performance of the proposed scheme is 129% faster than the advanced architecture of a previous proposal. Moreover, the number of the total memory references is reduced by 78.75% and 52.5% respectively compared to the basic and advanced architectures of the previous works.

Original languageEnglish
Title of host publicationProceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005
EditorsM.H. Hamza
Pages184-187
Number of pages4
Publication statusPublished - 2005 Dec 1
EventFourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005 - Cambridge, MA, United States
Duration: 2005 Oct 312005 Nov 2

Publication series

NameProceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005

Other

OtherFourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005
CountryUnited States
CityCambridge, MA
Period05-10-3105-11-02

Fingerprint

Adaptive filters
Data storage equipment
Processing
Embedded systems
Computer systems
Simulators

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Chen, C. M., Chen, C-H., Zeng, J. P., Chang, Y. P., & Tang, J. J. (2005). Alternative processing order with efficient architecture for adaptive deblocking filter in H.264/AVC. In M. H. Hamza (Ed.), Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005 (pp. 184-187). (Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005).
Chen, Chung Ming ; Chen, Chung-Ho ; Zeng, Jian Ping ; Chang, Yu Pin ; Tang, Jing Jou. / Alternative processing order with efficient architecture for adaptive deblocking filter in H.264/AVC. Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005. editor / M.H. Hamza. 2005. pp. 184-187 (Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005).
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title = "Alternative processing order with efficient architecture for adaptive deblocking filter in H.264/AVC",
abstract = "In this paper, we study and analyze the memory reference of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. In order to reduce the number of memory references and thus improve overall system performance in an embedded system, we propose an advanced filtering process order with an efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the performance of the proposed scheme is 129{\%} faster than the advanced architecture of a previous proposal. Moreover, the number of the total memory references is reduced by 78.75{\%} and 52.5{\%} respectively compared to the basic and advanced architectures of the previous works.",
author = "Chen, {Chung Ming} and Chung-Ho Chen and Zeng, {Jian Ping} and Chang, {Yu Pin} and Tang, {Jing Jou}",
year = "2005",
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language = "English",
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Chen, CM, Chen, C-H, Zeng, JP, Chang, YP & Tang, JJ 2005, Alternative processing order with efficient architecture for adaptive deblocking filter in H.264/AVC. in MH Hamza (ed.), Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005. Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005, pp. 184-187, Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005, Cambridge, MA, United States, 05-10-31.

Alternative processing order with efficient architecture for adaptive deblocking filter in H.264/AVC. / Chen, Chung Ming; Chen, Chung-Ho; Zeng, Jian Ping; Chang, Yu Pin; Tang, Jing Jou.

Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005. ed. / M.H. Hamza. 2005. p. 184-187 (Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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T1 - Alternative processing order with efficient architecture for adaptive deblocking filter in H.264/AVC

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N2 - In this paper, we study and analyze the memory reference of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. In order to reduce the number of memory references and thus improve overall system performance in an embedded system, we propose an advanced filtering process order with an efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the performance of the proposed scheme is 129% faster than the advanced architecture of a previous proposal. Moreover, the number of the total memory references is reduced by 78.75% and 52.5% respectively compared to the basic and advanced architectures of the previous works.

AB - In this paper, we study and analyze the memory reference of deblocking filter in H.264/AVC baseline decoder based on SimpleScalar/ARM simulator. In order to reduce the number of memory references and thus improve overall system performance in an embedded system, we propose an advanced filtering process order with an efficient VLSI architecture which simultaneously processes the horizontal filtering of vertical edge and vertical filtering of horizontal edge. As a result, the performance of the proposed scheme is 129% faster than the advanced architecture of a previous proposal. Moreover, the number of the total memory references is reduced by 78.75% and 52.5% respectively compared to the basic and advanced architectures of the previous works.

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Chen CM, Chen C-H, Zeng JP, Chang YP, Tang JJ. Alternative processing order with efficient architecture for adaptive deblocking filter in H.264/AVC. In Hamza MH, editor, Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005. 2005. p. 184-187. (Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005).