@inproceedings{192ec05d6e3a47b49c68eb37ad87b9be,
title = "An 8-bit 400-MS/s calibration-free SAR ADC with a pre-amplifier-only comparator",
abstract = "A single-channel lb/cycle 8-bit 400-MS/s successive-approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. The operation speed is enhanced by using the loop-unrolled technique in the coarse conversions. Moreover, we propose a timing control scheme which would shorten the critical timing path to alleviate the speed limitation in the fine conversions. Also, we propose a high-gain dynamic pre-amplifier to realize such a timing control scheme so as to meet our target resolution. The proof-of-concept prototype was fabricated in a TSMC 90-nm CMOS technology. At 1.2-V supply voltage and 400-MS/s sampling rate, the power consumption of the SAR ADC is 3.198 mW. The peak ENOB is 7.15 bits without costly calibration circuit. It achieves a figure of merit (FoM) of 56.29 fJ/conversion-step.",
author = "Hou, {Chih Huei} and Chang, {Soon Jyh} and Wu, {Hao Sheng} and Hu, {Huan Jui} and Cun, {En Ze}",
note = "Funding Information: This work is supported by National Science Council. The authors would like to express their gratitude to National Chip Implementation Center, Taiwan, for the chip fabrication and measurement support. Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 ; Conference date: 24-04-2017 Through 27-04-2017",
year = "2017",
month = jun,
day = "5",
doi = "10.1109/VLSI-DAT.2017.7939660",
language = "English",
series = "2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017",
address = "United States",
}