An adaptive code rate EDAC scheme for random access memory

Ching Yi Chen, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

As the VLSI technology scaling continues and the device dimension keeps shrinking, memories are more and more sensitive to soft errors. Memory cores usually occupy a large portion of an SOC and have significant impact on the chip reliability. Therefore error detection and correction (EDAC) techniques are commonly used for protecting the system against soft errors. This paper presents a novel EDAC scheme, which provides adaptive code rate for random access memories (RAMs). Under a certain reliability restriction, the proposed design allows more error bits than a conventional EDAC design.

Original languageEnglish
Title of host publicationDATE 10 - Design, Automation and Test in Europe
Pages735-740
Number of pages6
Publication statusPublished - 2010 Jun 9
EventDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010 - Dresden, Germany
Duration: 2010 Mar 82010 Mar 12

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Conference

ConferenceDesign, Automation and Test in Europe Conference and Exhibition, DATE 2010
CountryGermany
CityDresden
Period10-03-0810-03-12

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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