An advanced 3D format generation architecture for video and depth

Pin Chen Kuo, Kuan Ting Lee, Ching Lun Chou, Chun Wei Chang, Bin Da Liu, Jar Ferr Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, a hardware design for packing and depacking the 2D frame-compatible format suggested in [1] is proposed. Compared to the previous format that uses one view with one depth, the advanced 2D-compatible format reduces the bitrates of both the color and depth frames. For hardware costs, the operation frequency can reach 166.56 MHz, which can support maximum frame size up to FHD in real time.

Original languageEnglish
Title of host publication2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages654-657
Number of pages4
ISBN (Electronic)9781509015702
DOIs
Publication statusPublished - 2017 Jan 3
Event2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of
Duration: 2016 Oct 252016 Oct 28

Publication series

Name2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

Other

Other2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
CountryKorea, Republic of
CityJeju
Period16-10-2516-10-28

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Signal Processing

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  • Cite this

    Kuo, P. C., Lee, K. T., Chou, C. L., Chang, C. W., Liu, B. D., & Yang, J. F. (2017). An advanced 3D format generation architecture for video and depth. In 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 (pp. 654-657). [7804082] (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2016.7804082